Image Number 8 for United States Patent #5885852.
For manufacturing a packaged semiconductor device, a lead frame with an electrically insulating strip member and a semiconductor chip is placed in a molding unit having upper and lower dies. The upper and lower dies have recessed areas for determining a size of a cavity of the molding unit different from each other, the size of the cavity being measured in a direction perpendicular to a clamping motion direction of the dies. The lead frame is positioned so that a surface of each lead with the insulating strip member applied thereto is contacted with one of the upper and lower dies having a larger recessed area and a molding line of the molding unit intersects the insulating strip member. The molding unit is closed to clamp the lead frame to depress and thrust into spaces between adjacent leads that part of the strip member which is outside the molding line and to form the cavity of the molding unit. By injecting a molding material into the cavity, a molding package is provided encapsulating the semiconductor chip and a portion of each lead. The packaged semiconductor device has a flanged side surface with an insulating strip provided between a step of the flanged side surface and intermediate portions of the leads which are between first portions of the leads encapsulated in the molding package and second portions of the leads protruding from the flanged side surface.