Resources Contact Us Home
Semiconductor memory device and a reading method thereof

Image Number 2 for United States Patent #5883851.

In a semiconductor memory device, there is provided a column detecting circuit for generating a detection signal DETIO when respective voltage levels on a pair of I/O lines IO and IOB are developed into predetermined voltage levels which can be sensed as a valid data by external circuitry. Thereafter, a block selecting circuit and a sensing control signal generating circuit are respectively disabled by the detection signals DETIO and DETIOB causing a bit line precharge operation to be performed during a reading operation Thus, the sensing consumed by sense amplifiers during the reading operation period is reduced. In addition, since the bit line precharge operation is performed during the reading operation period, the bit line precharge time is reduced.

  Recently Added Patents
Message processing method and apparatus based on the SIP protocol and an IP communication system
PC secure video path
Biomarkers of gastric cancer and use thereof
Front exterior of an automotive tail lamp
Formwork release composition and use thereof
Dehydratable hygiene articles
Medicament delivery device and a method of medicament delivery
  Randomly Featured Patents
Imaging device having a capability of checking connection with a flash unit, flash unit having a capability of checking connection with an imaging device, and system including an imaging devic
Chip-packaging substrate and test method therefor
Hiding and detecting auxiliary data in media materials and signals
Magnetic resonance gyroscope with spectral control
Energy control device
Fragrance towelette
Clamp-on current sensor
Sealing subterranean zones
Systems, methods, and apparatuses for linear polar transmitters
Two station robotic welder