Resources Contact Us Home
Semiconductor memory device and a reading method thereof

Image Number 2 for United States Patent #5883851.

In a semiconductor memory device, there is provided a column detecting circuit for generating a detection signal DETIO when respective voltage levels on a pair of I/O lines IO and IOB are developed into predetermined voltage levels which can be sensed as a valid data by external circuitry. Thereafter, a block selecting circuit and a sensing control signal generating circuit are respectively disabled by the detection signals DETIO and DETIOB causing a bit line precharge operation to be performed during a reading operation Thus, the sensing consumed by sense amplifiers during the reading operation period is reduced. In addition, since the bit line precharge operation is performed during the reading operation period, the bit line precharge time is reduced.

  Recently Added Patents
Polar nematic compounds
Granulated sweetening composition
Distributed mobile access point acquisition
Voltage level shift circuits and methods
Message value indicator
Touch-sensitive device and communication device
System and method for data reconfiguration in an optical communication network
  Randomly Featured Patents
Method and apparatus for heat processing pulverized brown coal
Digital display jitter correction apparatus and method
Vibratory screen assemblies
Kinetic sculpture
Ring binder
Method of harmonic noise attenuation in correlated sweep data
Method of making aromatization particles containing coffee aroma constituents
Bubble level
Method of manufacturing games rackets
Method and apparatus for translating variable names to column names for accessing a database