Resources Contact Us Home
Semiconductor memory device and a reading method thereof

Image Number 2 for United States Patent #5883851.

In a semiconductor memory device, there is provided a column detecting circuit for generating a detection signal DETIO when respective voltage levels on a pair of I/O lines IO and IOB are developed into predetermined voltage levels which can be sensed as a valid data by external circuitry. Thereafter, a block selecting circuit and a sensing control signal generating circuit are respectively disabled by the detection signals DETIO and DETIOB causing a bit line precharge operation to be performed during a reading operation Thus, the sensing consumed by sense amplifiers during the reading operation period is reduced. In addition, since the bit line precharge operation is performed during the reading operation period, the bit line precharge time is reduced.

  Recently Added Patents
Analogue-to-digital converter
Hydroxyl-terminated thiocarbonate containing compounds, polymers, and copolymers, and polyurethanes and urethane acrylics made therefrom
Shallow trench media
Image heating device
Inter vehicle communication system
Sound producing apparatus for vehicle
System, method and computer program product for monitoring and controlling network connections from a supervisory operating system
  Randomly Featured Patents
Selectively liftable platform mechanism, and method for erecting a shooting house
Low volatile organic solvent based adhesive
Audible alarm unit
Fire hose locking device
Power amplification device
Method to prepare cyclopropenes
Method of routing and multiplexing demands in a telecommunications network
Socket wrench drill attachment
Capacitive pressure sensor and reference with stress isolating pedestal
5,6-epoxy-7-oxabicycloheptane substituted ethers useful in the treatment of thrombotic disease