Resources Contact Us Home

Image Number 14 for United States Patent #5867726.

A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

  Recently Added Patents
Bi-directional pattern dependent noise prediction
Entropy encoding and decoding using direct level and run-length/level context-adaptive arithmetic coding/decoding modes
Solid-state image sensing device and control method of solid-state image sensing device
Shallow trench media
Systems and methods for automobile accident claims initiation
Method of sheet alignment and method of post-processing comprising the same and method of image formation
Determination method for a reinitialization of a temporal sequence of fluoroscopic images of an examination region of an examination object
  Randomly Featured Patents
Mounting apparatus in support of a device from a platform
Selectable markers for yeast transformation
Commercial laundry heat recovery system
Three-dimensional perfumed seal
Signal processors for one bit signals
Method for determining threshold voltage variation using a device array
.alpha.-(Etherified oximino) carboxylic acids and acid chlorides
Automatic packaging machine
Synthetic papers and method of making the same
Cam-lock rocket securing mechanism