Resources Contact Us Home

Image Number 14 for United States Patent #5867726.

A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

  Recently Added Patents
Telecommunications system and method
Measurement system service for a vehicle instrument panel
Keyswitch controller
Printing system, information processing apparatus, print job processing method, information processing method, program, and storage medium
Automated security analysis for federated relationship
Para-xylylene based microfilm elution devices
Method and apparatus for editing a program on an optical disc
  Randomly Featured Patents
Combined topical and systemic method of administration of cyclosporine
Mobile telephone location process making use of handoff data
Composition and method for selective boronizing
Method and apparatus for processing print jobs via parallel spooling and despooling operations
System and method for combining multiple physical layer transport links
Subsurface drainage system and drain structure therefor
Levered connector extractor
Composite femoral implant having increased neck strength
Flat panel display