Resources Contact Us Home

Image Number 14 for United States Patent #5867726.

A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

  Recently Added Patents
Selecting modulation and coding scheme in the presence of interference
Modular authoring and visualization of rules using trees
Fused thiazole derivatives as kinase inhibitors
Stand for food service
Inhibitors of bacterial tyrosine kinase and uses thereof
Method and system for remapping processing elements in a pipeline of a graphics processing unit
Integrating map-reduce into a distributed relational database
  Randomly Featured Patents
Cookware lid
System and process for muting audio transmission during a computer network-based, multi-party teleconferencing session
Internal-combustion engine having a pre-combustion chamber
Grill brush
Magnetic transfer apparatus
Prisoner seat security device
Conveyor belt with advertising and method of making same
Engine mount assembly
Phase sensitive detector