Resources Contact Us Home

Image Number 14 for United States Patent #5867726.

A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

  Recently Added Patents
Electrophoretic element and display device
Categorization of design rule errors
System and method for transferring data in storage controllers
Synchronization scheduling apparatus and method in real-time multi-core system
Precision geolocation of moving or fixed transmitters using multiple observers
Stock analysis method, computer program product, and computer-readable recording medium
Trading related to fund compositions
  Randomly Featured Patents
Scale dissolver fluid
Environmental radiation detection via thermoluminescence
Flexible horseshoe
Video game machine
Method of stabilizing organic substrate materials including photographic dye images to light and a photographic material so stabilized
Popcorn popping machines and associated methods of manufacture and use
Shipping unit for non-riding lawn mower or the like
Parking track component
Electronic device, method of manufacturing the same, display and sensor