Resources Contact Us Home

Image Number 14 for United States Patent #5867726.

A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

  Recently Added Patents
Method and system for providing magnetic junctions having improved characteristics
Heat shield and laminated glass
Tablet computer
Antenna device
Multistable electromagnetic actuators
Range extension techniques for a wireless local area network
Lead with lead stiffener for implantable electrical stimulation systems and methods of making and using
  Randomly Featured Patents
Piperidine containing stabilizer compounds
Aminobenzophenones as inhibitors of interleukin and TNF
Conformable high temperature resistant tapes
Tent frame binding device
Control panel overlay
Optical communication system with improved maintenance capabilities
Stylus pen for capacitive type touch panel
Selective NPY (Y5) antagonists
Progressive categoration and treatment of refund abusers
Reset circuit with transient detection function