Resources Contact Us Home

Image Number 14 for United States Patent #5867726.

A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

  Recently Added Patents
Communication device and two-dimensional communication system using the same
Methods circuits apparatuses and systems for facilitating access to online content
Image enhancement based on multiple frames and motion estimation
Method and system for reciprocal mixing cancellation of wideband modulated blockers
Duty cycle adjustment of remote illumination source to maintain illumination output
Printed circuit board including electromagnetic bandgap structure
Methods and apparatus for mitigating interference between co-located collaborating radios
  Randomly Featured Patents
Cold storage warehouse with cryogenic test site
Barrier membrane
System for on demand task optimization
Valve lock
African violet plant named Monique
Electroless plating process employing non-noble metal hydrous oxide catalyst
Mechanical vehicle positioning device
Campylobacter glycosyltransferases for biosynthesis of gangliosides and ganglioside mimics
Fifth wheel assembly
Method of forming a blind solder joint in an ignition coil