Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Microcomputer










Image Number 14 for United States Patent #5867726.

A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.








 
 
  Recently Added Patents
Autobrake and decel control built-in test equipment
Bread basket
Communication terminal device, and recording medium
Systems and methods for advertising on content-screened web pages
Inter-cell power control in the presence of fractional frequency reuse
Cathode material for lithium ion secondary battery and lithium ion secondary battery using it
Terminal device, system and computer readable medium
  Randomly Featured Patents
State machine design for generating empty and full flags in an asynchronous FIFO
Amine phosphate containing photogenerating layer photoconductors
Polymer supports for nucleic acid synthesis
Azolylamine derivative
Glass pulverizer
Lens protection structure for miniature lens focusing mechanism
Vaccination and methods against diseases resulting from pathogenic responses by specific T cell populations
Electronic photographing device
Adjustable article mounting bracket
Oilwell tubular connection