Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Microcomputer










Image Number 14 for United States Patent #5867726.

A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.








 
 
  Recently Added Patents
Preserving and handling native data in hybrid object trees
Method and system for utilizing Perovskite material for charge storage and as a dielectric
Distylium plant named `PIIDIST-I`
Comb
Implicit certificate scheme
Voltage level shift circuits and methods
Systems and methods for reducing narrow bandwidth interference contained in broad bandwidth signals
  Randomly Featured Patents
Method for making multicolored foam and product thereof
Autonomous robot charging stations and methods
Diaper changing restraint system
Process and apparatus for applying liquid to web material
Novel radioassay procedure
Coffee vending machine
Cytokine suppressive anti-inflammatory drug binding protein
Ice auger attachment
Indium doped gallium arsenide crystals and method of preparation
Raster microscope