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Semiconductor memory using select transistors coupled to sub-bitlines from different blocks










Image Number 18 for United States Patent #5852570.

The semiconductor memory device of the invention includes: a semiconductor substrate; a first block; a second block adjacent to the first block; a main bitline; a first auxiliary conductive region; a first select transistor; and a first select line. The first block includes a first memory transistor having a first electrode, a second electrode and a gate electrode; a first sub-bitline including a part functioning as the first electrode of the first memory transistor; a second sub-bitline including a part functioning as the second electrode of the first memory transistor; and a first word line including a part functioning as the gate electrode of the first memory transistor, while the second block includes: a second memory transistor having a third electrode, a fourth electrode and a gate electrode; a third sub-bitline including a part functioning as the third electrode of the second memory transistor; a fourth sub-bitline including a part functioning as the fourth electrode of the second memory transistor; and a second word line including a part functioning as the gate electrode of the second memory transistor.








 
 
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