Resources Contact Us Home
High-performance fault tolerant computer system with clock length synchronization of loosely coupled processors

Image Number 10 for United States Patent #5845060.

A fault-tolerant computer system employing multiple CPUs executing the same instruction stream under independent clock cycle timing. The CPUs deterministically execute the instructions internally until input or output operations require access to memory or devices which are not synchronous with the local CPU clock. The CPUs are forced to take the same number of CPU clock cycles to complete the I/O operations. When the I/O operation is complete the internal processing of the instruction stream continues in a manner which is clock aligned in each of the multiple CPUs but which may be separate in real time due to oscillator drift. Accumulated drift is periodically removed by a timed interrupt which forces resynchronization of the CPUs in real time.

  Recently Added Patents
Developing device
Authentication service
Polarization preserving front projection screen microstructures
Antibodies to non-functional P2X.sub.7 receptor
Calendar integration methods and systems for presentation of events having combined activity and location information
Mass spectrometry method
Vehicle window opening and closing control device
  Randomly Featured Patents
Multiple-phase flow meter
Picture-in-picture television receiver with separate channel display
Box composed of pressed materials for shipping fruits, vegetables
Capsicum based insecticide and method of use
Local interconnection process for preventing dopant cross diffusion in shared gate electrodes
Air-powered vacuum cleaner floor tool
Device and method for determining tissue thickness and creating cardiac ablation lesions
Seating device
Obstacle warning system for a vehicle
Image forming apparatus which adds identification information to recorded images to prevent forgery