Resources Contact Us Home
High-performance fault tolerant computer system with clock length synchronization of loosely coupled processors

Image Number 10 for United States Patent #5845060.

A fault-tolerant computer system employing multiple CPUs executing the same instruction stream under independent clock cycle timing. The CPUs deterministically execute the instructions internally until input or output operations require access to memory or devices which are not synchronous with the local CPU clock. The CPUs are forced to take the same number of CPU clock cycles to complete the I/O operations. When the I/O operation is complete the internal processing of the instruction stream continues in a manner which is clock aligned in each of the multiple CPUs but which may be separate in real time due to oscillator drift. Accumulated drift is periodically removed by a timed interrupt which forces resynchronization of the CPUs in real time.

  Recently Added Patents
Electronic devices with voice command and contextual data processing capabilities
Computer system for routing package deliveries
Sequential control device for a striking mechanism
Human renal disease marker substance
Methods and systems for sending messages regarding an emergency that occurred at a facility
2,4-disubstituted pyrimidines useful as kinase inhibitors
Methods and systems for time-shifting content
  Randomly Featured Patents
Method of applying a super-absorbent composition to tissue or towel substrates
Apparatus and method for sealing and cutting tissue
Method for managing a group in a star network and apparatus using the method
System and method for transmitting control information between a control unit and at least one sub-unit
Method of balancing the bandwidth of a dual-mode filter
Hydrometer for determination of immunoglobulin content of mare colostrum
Gramercy dresser
Joint structure for jointing metal pipes at their ends
Aromatic copolyether sulfones
Interior decorative material having a tatami facing