Resources Contact Us Home
High-performance fault tolerant computer system with clock length synchronization of loosely coupled processors

Image Number 10 for United States Patent #5845060.

A fault-tolerant computer system employing multiple CPUs executing the same instruction stream under independent clock cycle timing. The CPUs deterministically execute the instructions internally until input or output operations require access to memory or devices which are not synchronous with the local CPU clock. The CPUs are forced to take the same number of CPU clock cycles to complete the I/O operations. When the I/O operation is complete the internal processing of the instruction stream continues in a manner which is clock aligned in each of the multiple CPUs but which may be separate in real time due to oscillator drift. Accumulated drift is periodically removed by a timed interrupt which forces resynchronization of the CPUs in real time.

  Recently Added Patents
Image processing apparatus and image processing method
Real ear measurement system using thin tube
Pose-variant face recognition using multiscale local descriptors
Dual-box location aware and dual-bitmap voltage domain aware on-chip variation techniques
Apparatus and method for transferring a data signal propagated along a bidirectional communication path within a data processing apparatus
Protective vest
  Randomly Featured Patents
Removable memory card for use with portable electronic devices
Ribbon overbraid cable
Multidirectional cluster lights for motor vehicles
Acoustic transducer for automotive noise cancellation
Neoplasm specific antibodies and uses thereof
Digital TV receiving smart antenna control system and controlling method of the same
Liquid crystal display and fabricating method thereof
Ski binding
Cover for collapsing board
Mobile phone