Image Number 14 for United States Patent #5812475.
A self refresh circuit for an integrated circuit memory device includes a programmable refresh circuit, a plurality of counters, and a refresh cycle selection circuit. The programmable refresh circuit can be electrically programmed to generate one of a plurality of refresh control signals. A first one of the counters generates a first oscillating output signal having a first predetermined period and each successive counter generates a respective oscillating output signal having a respective period twice that of a respective preceding counter. The refresh cycle selection circuit selects a self refresh cycle from one of the oscillating output signals in response to the refresh control signal generated by the at least one programmable refresh circuit. Related methods are also disclosed.