Image Number 18 for United States Patent #5796129.
A master slice type gate array has a plurality of block areas. Each block area includes a plurality of basic cells arranged in a matrix. Different block areas have transistors with different channel widths. Within each of the block areas, a plurality of basic cells are connected to one another through a wiring layer to form function cells. First layer wirings for the function cells are completed within an area between rows of power source wirings Vdd and Vss of the first layer in the transverse direction. Contacts for connecting the sources and drains of P- and N-channel type MOS transistors to the first layer wirings are arranged in rows. Even if the channel widths are changed, the position of the contacts for forming the function cells and the wiring pattern remain unchanged for every block. Therefore, the master slice type gate array can be optimized for various performance parameters such as speed, integration, power consumption and other factors. As a result, the number of steps required to arrange the function cells can be reduced.