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Image Number 13 for United States Patent #5784331.
A memory circuit has a plurality of data storage locations and an address associated with each data storage location. A first decoded address storage circuit stores a first decoded memory address and outputs the stored first decoded memory address. A second decoded address storage circuit stores a second decoded memory address and outputs the stored second decoded memory address. An address access circuit is coupled to the output of the first decoded address storage circuit and accesses the data storage location associated with the first decoded memory address in response to the first decoded memory address being output from the first decoded address storage circuit. A control circuit is coupled to the first decoded address storage circuit for controlling the transfer of decoded memory address information from the second decoded address storage circuit to the first decoded address storage circuit.
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