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Self-test circuit for memory integrated circuits










Image Number 6 for United States Patent #5754486.

A sense amplifier senses and stores data from a memory cell in an array of memory cells arranged in rows and columns. The sense amplifier includes a sense circuit having a pair of first and second complementary digit lines which senses a voltage differential between the first and second complementary digit lines and in response to the sensed voltage differential drives the first and second complementary digit lines to voltage levels corresponding to complementary logic states. An isolation circuit is coupled between the pair of first and second complementary digit lines of the sense amplifier and a pair of first and second complementary digit lines associated with a column of memory cells. The isolation circuit is operable to couple the first complementary digit line of the sense amplifier to the first complementary digit line of the column of memory cells and the second complementary digit line of the sense amplifier to the secondary complementary digit line of the column of memory cells. A switch circuit is operable to couple the first complementary digit line of the sense amplifier to the second complementary digit line of the column of memory cells, and the second complementary digit line of the sense amplifier to the first complementary digit line of the column of memory cells. An equilibration circuit is coupled between the pair of complementary digit lines of the column of memory cells and is operable to equalize the voltage level on the digit lines to a predetermined level.








 
 
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