Resources Contact Us Home
Floating gate type non-volatile semiconductor memory device

Image Number 5 for United States Patent #5751036.

A tunnel region is surrounded by an impurity diffusion layer and a drain diffusion layer, and a coupling portion coupling one and the other end portions of a floating gate to each other is arranged on only an isolation region. With this arrangement, even if a parasitic inversion layer is formed below the other end portion upon extraction of electrons, the parasitic inversion layer does not contact a semiconductor substrate, resulting in a small substrate current. Therefore, a high-voltage, large-current external power supply need not be prepared in addition to a normal voltage power supply.

  Recently Added Patents
Detachable racquet weight
Business method for charitable fund raising
Low latency, high bandwidth data communications between compute nodes in a parallel computer
Method of compensating for nonlinearity in a DFE-based receiver
Methods and systems for full-color three-dimensional image display
System and method for efficient interpretation of natural images and document images in terms of objects and their parts
User equipment terminal, base station and control information transmission method
  Randomly Featured Patents
Method and apparatus for reducing iron-oxides-particles having a broad range of sizes
Soybean cultivar CX433RR
Thermal decay time logging method
Gear box
All-terrain berm
Correcting device for the combustion of engines of vehicles during transitional phases of operation
Anti-snoring formulations using yohimbine
Electric rotating machine
Electronic transmission shift control
Audio encoder