Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Floating gate type non-volatile semiconductor memory device










Image Number 5 for United States Patent #5751036.

A tunnel region is surrounded by an impurity diffusion layer and a drain diffusion layer, and a coupling portion coupling one and the other end portions of a floating gate to each other is arranged on only an isolation region. With this arrangement, even if a parasitic inversion layer is formed below the other end portion upon extraction of electrons, the parasitic inversion layer does not contact a semiconductor substrate, resulting in a small substrate current. Therefore, a high-voltage, large-current external power supply need not be prepared in addition to a normal voltage power supply.








 
 
  Recently Added Patents
Antimony and germanium complexes useful for CVD/ALD of metal thin films
Subband SNR correction in a frequency selective scheduler
Controller with screen
Systems and methods for sorting particles
Automatic logical position adjustment of multiple screens
Subcarrier cluster-based power control in wireless communications
Haworthia plant named `CAPETOWN`
  Randomly Featured Patents
Hole card reader
Method of wiring semiconductor device using energy beam
Pumpkin carver
Crawler-mounted conveying train
Acyl derivatives of tris-hydroxy-ethyl-perhydro-1,3,5-triazine
Apparatus for and method of recording and reproducing holograms
Associating network and storage activities for forensic analysis
Minibar system
System development and debug tools for power management functions in a computer system
Solar cell module provided with a heat-fused portion