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Floating gate type non-volatile semiconductor memory device










Image Number 5 for United States Patent #5751036.

A tunnel region is surrounded by an impurity diffusion layer and a drain diffusion layer, and a coupling portion coupling one and the other end portions of a floating gate to each other is arranged on only an isolation region. With this arrangement, even if a parasitic inversion layer is formed below the other end portion upon extraction of electrons, the parasitic inversion layer does not contact a semiconductor substrate, resulting in a small substrate current. Therefore, a high-voltage, large-current external power supply need not be prepared in addition to a normal voltage power supply.








 
 
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