Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Floating gate type non-volatile semiconductor memory device










Image Number 5 for United States Patent #5751036.

A tunnel region is surrounded by an impurity diffusion layer and a drain diffusion layer, and a coupling portion coupling one and the other end portions of a floating gate to each other is arranged on only an isolation region. With this arrangement, even if a parasitic inversion layer is formed below the other end portion upon extraction of electrons, the parasitic inversion layer does not contact a semiconductor substrate, resulting in a small substrate current. Therefore, a high-voltage, large-current external power supply need not be prepared in addition to a normal voltage power supply.








 
 
  Recently Added Patents
Illuminating waveguide fabrication method
Biodegradable aliphatic-aromatic copolyester for use in nonwoven webs
Cooling method and device for cooling a medium-voltage electrical installation in a protective sheath
Millimeter wave imaging method and system to detect concealed objects
Vehicle detection apparatus and method using magnetic sensor
Pet carrier
Arrays of optical confinements and uses thereof
  Randomly Featured Patents
Foldable vehicle seat
Apparatus for improving the optical intensity induced damage limit of optical quality crystals
Embossed tissue sheet
Paper sheet processing apparatus
Process for the selective extracorporeal precipitation of low-density lipoproteins
Collapsible baseball equipment hangar apparatus
Image resolution enhancement technology (IRET) for dual dye-load inkjet printer
Stretcher
Method for manufacturing a semiconductor device having a III-V nitride semiconductor
Armless chair