Resources Contact Us Home
Floating gate type non-volatile semiconductor memory device

Image Number 5 for United States Patent #5751036.

A tunnel region is surrounded by an impurity diffusion layer and a drain diffusion layer, and a coupling portion coupling one and the other end portions of a floating gate to each other is arranged on only an isolation region. With this arrangement, even if a parasitic inversion layer is formed below the other end portion upon extraction of electrons, the parasitic inversion layer does not contact a semiconductor substrate, resulting in a small substrate current. Therefore, a high-voltage, large-current external power supply need not be prepared in addition to a normal voltage power supply.

  Recently Added Patents
Scaleable status tracking of multiple assist hardware threads
Multi-contoured yoga support
Scanning transmission electron microscope and axial adjustment method thereof
Soliciting first party in communication session to maintain call when degradation of connection to second party is anticipated
Random sampling for geophysical acquisitions
Hand mixer
Low drop-out regulator providing constant current and maximum voltage limit
  Randomly Featured Patents
Longitudinally flexible stent
Process for producing an allergen extract
Rice lossless compression module
Remote identification of explosives and other harmful materials
Side channel clarifier
Image forming apparatus that uses fixing member temperature or thickness of recording medium to detect when to halt the rotation drive of a fixing member drive unit
Thin-film window for nuclear instruments and method of making same
Alkylation by controlling olefin ratios
Method for evaluation of a gemstone
Multi-beam scanning optical system and image forming apparatus using the same