Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Floating gate type non-volatile semiconductor memory device










Image Number 5 for United States Patent #5751036.

A tunnel region is surrounded by an impurity diffusion layer and a drain diffusion layer, and a coupling portion coupling one and the other end portions of a floating gate to each other is arranged on only an isolation region. With this arrangement, even if a parasitic inversion layer is formed below the other end portion upon extraction of electrons, the parasitic inversion layer does not contact a semiconductor substrate, resulting in a small substrate current. Therefore, a high-voltage, large-current external power supply need not be prepared in addition to a normal voltage power supply.








 
 
  Recently Added Patents
Satellite mounting pole
Power converter and method including noise suppression by controlling phase shifting of converter cells
Evaluation compiler method
Method and device for authenticating transmitted user data
System for and method of remotely auditing inventoried assets
(4947
Processor and data transfer method
  Randomly Featured Patents
Pressure biased lubricant valve
Liquid developer and a method of forming image
Programmable logic device and method for designing the same
Outer wall structure of a torque converter and others
Embedded license data file distribution and processing system
Memory address decode array with vertical transistors
Automatic reference voltage regulation in a memory device
Telephone handset cover
Method and apparatus for synchronizing device information
System for reducing signal interference in modulated signal communication