Image Number 3 for United States Patent #5745373.
A logic circuit generating method and apparatus generating logic circuits of a circuit system by minimizing the fan-out count of cells or cell macros constituting information specific to the circuit system. According to the method, a Boolean expression and the polarities of its input/output variables are input from a design master file of the apparatus. The Boolean expression is then transformed into a two-branch tree composed of nodes represented by the logical operators of that expression. In the two-branch tree, the nodes representing a parent and a child logical operator are converted into a single node, whereby a multiple-branch tree is generated. That is, a plurality of gates are connected to a single net, or signal line. A cell library is referenced so that cells are assigned initially to the multiple-branch tree thus obtained. The initial cell assignment is performed preferentially starting from the cell whose fan-out count is the largest. This is done to minimize the number of loads represented by the assigned cells (i.e., the number of cells connected to the output net). The number of gate stages is then evaluated. The stage count is minimized by reassigning the cells. Finally, the acquired gate logic is output to the design master file.