Resources Contact Us Home
Process for global planarization of memory and globally planarized memory

Image Number 6 for United States Patent #5731234.

A process for the global planarization of a memory circuit and globally planarized memory. The process includes defining a memory cell circuit area and a peripheral circuit area on a silicon substrate. A memory cell MOS transistor is formed in the memory cell circuit area and at least two peripheral circuit MOS transistors are formed in the peripheral circuit area. A memory cell electronic component is then formed in the memory cell circuit area and in the peripheral circuit area from a plurality of thin film layers. The thin film layers are defined in the peripheral circuit area such that an open circuit is formed between the thin film layers and the peripheral circuit MOS transistors. A planarized insulating layer is then formed on top of the silicon substrate.

  Recently Added Patents
Hand warmer
Wireless communication device that transmits geographic location information in router advertisement acknowledgement messages
Electrode including silicon-comprising fibres and electrochemical cells including the same
Adaptive transmissions in wireless networks
Mechanical pitch shifter
Interpenetrating polymer network and method for making the same
  Randomly Featured Patents
Spring actuated chop sticks
Lens-fitted film unit with IC memory and method of writing data in IC memory
Electrical separator apparatus and method of counterflow gradient focusing
Novel hydroxy substituted prostanoic acids, esters, congeners, intermediates and process
Bounding I/O service time
Gamma camera with reflectivity mask
Drilling restart control system
Glucuronide metabolites and epimers thereof of tigecycline
Treated textiles