Resources Contact Us Home
Process for global planarization of memory and globally planarized memory

Image Number 6 for United States Patent #5731234.

A process for the global planarization of a memory circuit and globally planarized memory. The process includes defining a memory cell circuit area and a peripheral circuit area on a silicon substrate. A memory cell MOS transistor is formed in the memory cell circuit area and at least two peripheral circuit MOS transistors are formed in the peripheral circuit area. A memory cell electronic component is then formed in the memory cell circuit area and in the peripheral circuit area from a plurality of thin film layers. The thin film layers are defined in the peripheral circuit area such that an open circuit is formed between the thin film layers and the peripheral circuit MOS transistors. A planarized insulating layer is then formed on top of the silicon substrate.

  Recently Added Patents
Power surface mount light emitting die package
Method and apparatus for pre-scheduling in closed-loop MU-MIMO antenna system
Personal IP toll-free number
High-voltage AC light-emitting diode structure
Video processing system and device with encoding and decoding modes and method for use therewith
Supply voltage generating circuit and semiconductor device having the same
Device in a system operating with CAN-protocol and in a control and/or supervision system
  Randomly Featured Patents
Apparatus for applying magnetic liquid to moving web
Wide range digital meter
Soy proteins and/or soy derivatives with zero-valent iron compositions and use for environmental remediation
Crimp-free infusible reinforcement fabric and composite reinforced material therefrom
LED light emitting device and method of driving the same
Method of fabricating high performance BiCMOS structures having poly emitters and silicided bases
Purification process for MDA
Heavy duty fabric softening laundry detergent composition
Cellulose products treated with isocyanate compositions
Plate-type filter