Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Process for global planarization of memory and globally planarized memory










Image Number 6 for United States Patent #5731234.

A process for the global planarization of a memory circuit and globally planarized memory. The process includes defining a memory cell circuit area and a peripheral circuit area on a silicon substrate. A memory cell MOS transistor is formed in the memory cell circuit area and at least two peripheral circuit MOS transistors are formed in the peripheral circuit area. A memory cell electronic component is then formed in the memory cell circuit area and in the peripheral circuit area from a plurality of thin film layers. The thin film layers are defined in the peripheral circuit area such that an open circuit is formed between the thin film layers and the peripheral circuit MOS transistors. A planarized insulating layer is then formed on top of the silicon substrate.








 
 
  Recently Added Patents
Manufacturing aircraft parts
Method and apparatus for image sensor packaging
Method and apparatus for laser strip splicing
Method for radiation sterilization of medical devices
Bad column management with bit information in non-volatile memory systems
Variety corn line NPAA2720
Systems and methods for authorizing, authenticating and accounting users having transparent computer access to a network using a gateway device
  Randomly Featured Patents
Apparatus for recording and/or reading information on an optical record carrier provided with preformed tracks
Fipple block for musical recorders
Method for aligning film sheets and rectangular panels in display panel manufacturing system
Method of manufacturing optical crystal element of laser
Throw and catch toy
Device for protecting audio equipment in vehicle against theft
Controlled growth of gallium nitride nanostructures
Simulated rotating light for children's vehicles and the like
Low pressure switch/initiator/gas generator
Variable color display system for sequentially exhibiting digital values