Resources Contact Us Home
Process for global planarization of memory and globally planarized memory

Image Number 6 for United States Patent #5731234.

A process for the global planarization of a memory circuit and globally planarized memory. The process includes defining a memory cell circuit area and a peripheral circuit area on a silicon substrate. A memory cell MOS transistor is formed in the memory cell circuit area and at least two peripheral circuit MOS transistors are formed in the peripheral circuit area. A memory cell electronic component is then formed in the memory cell circuit area and in the peripheral circuit area from a plurality of thin film layers. The thin film layers are defined in the peripheral circuit area such that an open circuit is formed between the thin film layers and the peripheral circuit MOS transistors. A planarized insulating layer is then formed on top of the silicon substrate.

  Recently Added Patents
Human renal disease marker substance
Image forming apparatus
Method and apparatus for allocating and obtaining IP address
Method and apparatus for coordinating hopping of resources in wireless communication systems
Systems and methods for providing live voicemail to a mobile handset
Rewarding independent influencers
Method for making an abrasion-resistant steel plate and plate obtained
  Randomly Featured Patents
Image processing method and image forming apparatus
Pesticidal substituted 2-[6-(pyrimidinyl)-indol-1-yl]-acrylic esters
Printer with edge strip trimmer
Humidifiers for forced air systems
Device to receive, buffer, and transmit packets of data in a packet switching network
Natural circulation industrial boiler for steam assisted gravity drainage (SAGD) process
Method and system for providing a magnetic read transducer having a bilayer magnetic seed layer
Test device
Muting circuit for AM stereophonic receiver
Power module device