Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Process for global planarization of memory and globally planarized memory










Image Number 6 for United States Patent #5731234.

A process for the global planarization of a memory circuit and globally planarized memory. The process includes defining a memory cell circuit area and a peripheral circuit area on a silicon substrate. A memory cell MOS transistor is formed in the memory cell circuit area and at least two peripheral circuit MOS transistors are formed in the peripheral circuit area. A memory cell electronic component is then formed in the memory cell circuit area and in the peripheral circuit area from a plurality of thin film layers. The thin film layers are defined in the peripheral circuit area such that an open circuit is formed between the thin film layers and the peripheral circuit MOS transistors. A planarized insulating layer is then formed on top of the silicon substrate.








 
 
  Recently Added Patents
Device chip carriers, modules, and methods of forming thereof
Inhibitors of human immunodeficiency virus replication
Coordinated multi-point transmission in a cellular network
Smooth silicon-containing films
Vehicle having power supply apparatus
Method and CTDevice for computer tomographic spiral scanning of a patient
Soybean variety XB51J12
  Randomly Featured Patents
Method and system for providing message services in a communication system
Method for detecting a target nucleic acid sequence
Beverage brewing system including a liquid moving assembly
Fuchsia plant named `Kiefulap`
Method for explosive breaking of hard compact material
Method and apparatus for reducing the intensity of magnetic field emissions from video display units
Microcapillary devices using high dielectric constant materials and related methods
Coating solution and method for forming dielectric film
Telephone cable splices
Steam iron with calcification indication