Resources Contact Us Home
Process for global planarization of memory and globally planarized memory

Image Number 2 for United States Patent #5731234.

A process for the global planarization of a memory circuit and globally planarized memory. The process includes defining a memory cell circuit area and a peripheral circuit area on a silicon substrate. A memory cell MOS transistor is formed in the memory cell circuit area and at least two peripheral circuit MOS transistors are formed in the peripheral circuit area. A memory cell electronic component is then formed in the memory cell circuit area and in the peripheral circuit area from a plurality of thin film layers. The thin film layers are defined in the peripheral circuit area such that an open circuit is formed between the thin film layers and the peripheral circuit MOS transistors. A planarized insulating layer is then formed on top of the silicon substrate.

  Recently Added Patents
Context-based adaptive binary arithmetic coding engine
Semiconductor devices and methods for changing operating characteristics and semiconductor systems including the same
Synthetic refrigeration oil composition for HFC applications
Method of operating a split gate flash memory cell with coupling gate
Probe for ultrasound diagnostic apparatus
Systems and methods for processing telephone calls
Polyolefin and composition for pipe systems and sheets
  Randomly Featured Patents
Frame head jamb
Device for adjusting position of drive element for opening and closing automatically horizontally opening and closing sliding door
Methods and apparatus for balancing armatures during coil winding
Guard bed for removing contaminants from feedstock to a normal paraffin extraction unit
Combined water purifying beverage maker
Developing apparatus comprising developing roller that is rotated upward from below in developing area and image forming apparatus using the same
Optical fiber cable with plural modular bundles of hermtically sealed optical fibers inside an outer cable sheath
Adjustable electrical box assembly
Method for reducing DNS resolution delay
Low-cost universal drive for use with switched reluctance machines