Resources Contact Us Home
Process for global planarization of memory and globally planarized memory

Image Number 2 for United States Patent #5731234.

A process for the global planarization of a memory circuit and globally planarized memory. The process includes defining a memory cell circuit area and a peripheral circuit area on a silicon substrate. A memory cell MOS transistor is formed in the memory cell circuit area and at least two peripheral circuit MOS transistors are formed in the peripheral circuit area. A memory cell electronic component is then formed in the memory cell circuit area and in the peripheral circuit area from a plurality of thin film layers. The thin film layers are defined in the peripheral circuit area such that an open circuit is formed between the thin film layers and the peripheral circuit MOS transistors. A planarized insulating layer is then formed on top of the silicon substrate.

  Recently Added Patents
Device and method for controlling brightness of organic light emitting diode display
Distributed image acquisition, storage, and backup system
Circuit board and display panel assembly having the same
Split-ring resonator creating a photonic metamaterial
Method and apparatus for generating images using a color field sequential display
Instrumenting configuration and system settings
Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure
  Randomly Featured Patents
Method for producing a solid electrolyte cell
Valve actuator
Photographic film developing apparatus
Garden ball
Synthetic RF detection system and method
Process for preparing ether tricarboxylates
Tray device for wheelbarrows
Lepidopteran GABA gated chloride channel and nucleic acids encoding subunits thereof
Mine door system with trigger-actuated latch mechanism
Seamless integrated network system for wireless communication systems