Resources Contact Us Home
Process for global planarization of memory and globally planarized memory

Image Number 2 for United States Patent #5731234.

A process for the global planarization of a memory circuit and globally planarized memory. The process includes defining a memory cell circuit area and a peripheral circuit area on a silicon substrate. A memory cell MOS transistor is formed in the memory cell circuit area and at least two peripheral circuit MOS transistors are formed in the peripheral circuit area. A memory cell electronic component is then formed in the memory cell circuit area and in the peripheral circuit area from a plurality of thin film layers. The thin film layers are defined in the peripheral circuit area such that an open circuit is formed between the thin film layers and the peripheral circuit MOS transistors. A planarized insulating layer is then formed on top of the silicon substrate.

  Recently Added Patents
Gaze tracking password input method and device utilizing the same
Image coding apparatus and image decoding apparatus
System and method for enhanced transaction payment
Automated measurement of concentration and/or amount in a biological sample
Headset systems and methods
Imidazole derivatives used as TAFIa inhibitors
  Randomly Featured Patents
Charge/discharge protection circuit with latch circuit for protecting a charge control FET from overheating in a portable device
Apparatus for folding paper items
CMOS output buffer with enhanced high ESD protection capability
Electromagnetic wave frequency filter
Asymmetric porous adsorptive bead
Method and apparatus for indicating a temporary block flow to which a piggybacked acknowledgement/non-acknowledgement field is addressed
Function keys for a portable wireless telephone
Method of encapsulating packaged microelectronic devices with a barrier
Fiber lubricants derived from the oxyalkylation of a glycerol-1,3-dialkylether
Control device for vehicle