Resources Contact Us Home
Process for global planarization of memory and globally planarized memory

Image Number 2 for United States Patent #5731234.

A process for the global planarization of a memory circuit and globally planarized memory. The process includes defining a memory cell circuit area and a peripheral circuit area on a silicon substrate. A memory cell MOS transistor is formed in the memory cell circuit area and at least two peripheral circuit MOS transistors are formed in the peripheral circuit area. A memory cell electronic component is then formed in the memory cell circuit area and in the peripheral circuit area from a plurality of thin film layers. The thin film layers are defined in the peripheral circuit area such that an open circuit is formed between the thin film layers and the peripheral circuit MOS transistors. A planarized insulating layer is then formed on top of the silicon substrate.

  Recently Added Patents
Soliciting first party in communication session to maintain call when degradation of connection to second party is anticipated
Method and system for establishing security connection between switch equipments
Viruses lacking epithelial cell receptor entry
Web development environment that enables a developer to interact with run-time output presentation of a page
Inhibitor of casein kinase 1delta and casein kinase 1E
Single well reservoir characterization apparatus and methods
Conductive polymer and a solid electrolytic capacitor using the same as a solid electrolyte
  Randomly Featured Patents
Outer side portion of a brake rotor
.beta.-ketoacyl-ACP synthetase II enzymes and genes coding for same
Apparatus and method for initializing system global variables by using multiple load/store instructions
Electron and ion beam-shaping apparatus
Smart laser diode array assembly
System and method for timeslot and channel allocation
Data processing device
Purification of phosphoric acid with urea and nitric acid
Resonator filters with wide stopbands
Glass breaking machine