Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Process for global planarization of memory and globally planarized memory










Image Number 2 for United States Patent #5731234.

A process for the global planarization of a memory circuit and globally planarized memory. The process includes defining a memory cell circuit area and a peripheral circuit area on a silicon substrate. A memory cell MOS transistor is formed in the memory cell circuit area and at least two peripheral circuit MOS transistors are formed in the peripheral circuit area. A memory cell electronic component is then formed in the memory cell circuit area and in the peripheral circuit area from a plurality of thin film layers. The thin film layers are defined in the peripheral circuit area such that an open circuit is formed between the thin film layers and the peripheral circuit MOS transistors. A planarized insulating layer is then formed on top of the silicon substrate.








 
 
  Recently Added Patents
Communication device and two-dimensional communication system using the same
Wireless communications apparatus and wireless communications method
Methods of operating non-volatile memory devices during write operation interruption, non-volatile memory devices, memories and electronic systems operating the same
Salts and polymorphs of desazadesferrithiocin polyether analogues as metal chelation agents
Formulations, their use as or for producing dishwashing detergents and their production
Navigating applications using side-mounted touchpad
Channel marking for chip mark overflow and calibration errors
  Randomly Featured Patents
Non-air cooled radiant burner
Spinal fixation system
Lamp, reflector and grille interlock assembly
System and method of acoustic doppler beamforming
Applicator for applying a coating to a surface
Ink cartridge
Isotactic propylene copolymer fibers, their preparation and use
Voltage comparator
Transparent plastic packaging blister
Plural key actuated totalizer for gasoline sales pump