Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Process for global planarization of memory and globally planarized memory










Image Number 2 for United States Patent #5731234.

A process for the global planarization of a memory circuit and globally planarized memory. The process includes defining a memory cell circuit area and a peripheral circuit area on a silicon substrate. A memory cell MOS transistor is formed in the memory cell circuit area and at least two peripheral circuit MOS transistors are formed in the peripheral circuit area. A memory cell electronic component is then formed in the memory cell circuit area and in the peripheral circuit area from a plurality of thin film layers. The thin film layers are defined in the peripheral circuit area such that an open circuit is formed between the thin film layers and the peripheral circuit MOS transistors. A planarized insulating layer is then formed on top of the silicon substrate.








 
 
  Recently Added Patents
Method and apparatus for laser strip splicing
Manufacturing method power semiconductor device
Binary-to-gray converting circuits and gray code counter including the same
Video editing apparatus
Management of memory array with magnetic random access memory (MRAM)
Systems and methods for redox flow battery scalable modular reactant storage
Wide viewing angle indicators for network devices
  Randomly Featured Patents
Acid perm method
Dinosaur shaped food product
Separator and method for separation of oil, gas and water
Cable connector
Directional and limiting gate
Insulated gate semiconductor device and method of manufacturing the same
Mixed matrix membrane for gas separation
Nanometer-scale electromechanical switch and fabrication process
Variable length coder and data packing circuit
Universal subscriber communicator module