Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Address multiplex semiconductor memory device for enabling testing of the entire circuit or for only partial components thereof










Image Number 4 for United States Patent #5726994.

A memory array is logically and/or physically divided into a plurality of blocks to allow test by individual blocks. When a plurality of column address strobe signals are provided and memory accessing is made by a plurality of bits to the memory array corresponding to the column address strobe signal, tests are independently conducted for each memory array by using the column address strobe signal.








 
 
  Recently Added Patents
Normalized contextual performance metric for the assessment of fatigue-related incidents
System and method for distributed security
Method and apparatus for selective decoding in a wireless communication system
Method of forming micropattern, method of forming damascene metallization, and semiconductor device and semiconductor memory device fabricated using the same
Method and apparatus for cutting high quality internal features and contours
High power insulated gate bipolar transistors
Gate timing for short servo wedge in disk memory systems
  Randomly Featured Patents
High-speed bit synchronizer with multi-stage control structure
Assembly for LSI test and method for the test
Automatic gain control circuit
Monoperoxyphthalic acid bleaching composition containing DTPMP
Local area network connecting computer products via long telephone lines
Electronic game housing
Method for manipulating optical energy using poled structure
Internal combustion engine
Coating composition and antifouling paint
Spring ring and hat ring seal