Resources Contact Us Home
Address multiplex semiconductor memory device for enabling testing of the entire circuit or for only partial components thereof

Image Number 4 for United States Patent #5726994.

A memory array is logically and/or physically divided into a plurality of blocks to allow test by individual blocks. When a plurality of column address strobe signals are provided and memory accessing is made by a plurality of bits to the memory array corresponding to the column address strobe signal, tests are independently conducted for each memory array by using the column address strobe signal.

  Recently Added Patents
Critical word forwarding with adaptive prediction
Look up table (LUT) structure supporting exclusive OR (XOR) circuitry configured to allow for generation of a result using quaternary adders
System and method for detecting an earth ground fault of an external power supply connected to a vehicle
Managing method and apparatus for servicing contents provided by content provider
Sampling switch circuit that uses correlated level shifting
Method of making a CIG target by cold spraying
Anti-slip strip for vehicle running boards
  Randomly Featured Patents
Flame retardant thermoplastic resin composition
Knife handle
System and method for identifying conditions leading to a particular result in a multi-variant system
Process and apparatus for obtaining cambered glass sheets
Motivational and religious device and award
Pyrrolidone derivatives and memory enhancement use thereof
Process and apparatus for producing evaporated phosphor sheets and an evaporated phosphor sheet produced by means of such process and apparatus
Adjustable height insulation panel
Information streaming in a multi-process system using shared memory