Resources Contact Us Home
Address multiplex semiconductor memory device for enabling testing of the entire circuit or for only partial components thereof

Image Number 4 for United States Patent #5726994.

A memory array is logically and/or physically divided into a plurality of blocks to allow test by individual blocks. When a plurality of column address strobe signals are provided and memory accessing is made by a plurality of bits to the memory array corresponding to the column address strobe signal, tests are independently conducted for each memory array by using the column address strobe signal.

  Recently Added Patents
Ultrathin fluid-absorbent cores
Pattern generation method and pattern generation program
Managing personal information on a network
Range extension techniques for a wireless local area network
System and method for detecting crop rows in an agricultural field
Method and system for determining an optimal missile intercept approach direction for correct remote sensor-to-seeker handover
  Randomly Featured Patents
Binary fluid burner device with burner units combined which functions as if it were a single large-capacity burner
Optical system design for a universal computing device
Drill head
Instrument panel
Apparatus and method for retaining pleats in hanging draperies
Low phase noise recursive direct digital synthesis with automatic gain control gain stabilization
Linear valve actuator
Method and apparatus for adding commercial value to traffic control systems
Video projector type television receiver
Yellow couplers for photographic elements and processes