Resources Contact Us Home
Address multiplex semiconductor memory device for enabling testing of the entire circuit or for only partial components thereof

Image Number 4 for United States Patent #5726994.

A memory array is logically and/or physically divided into a plurality of blocks to allow test by individual blocks. When a plurality of column address strobe signals are provided and memory accessing is made by a plurality of bits to the memory array corresponding to the column address strobe signal, tests are independently conducted for each memory array by using the column address strobe signal.

  Recently Added Patents
Isoselective polymerization of epoxides
Integrated circuit with electromagnetic intrachip communication and methods for use therewith
Multiple CQI feedback for cellular networks
Intermediate film for laminated glasses, and laminated glass
Arbitration for memory device with commands
Method of treating a preceramic material
Electronic device package and fabrication method thereof
  Randomly Featured Patents
Flat-panel display apparatus
Receiving apparatus and receiving method, and program
Method and system for extraction of liquid hydraulics from subterranean wells
Method and system for estimating power consumption of integrated circuitry
Injection pump
Pressure indicator for measurement of hot pressure mediums
Epothilone derivatives and methods for making and using the same
Facilitating display of an interactive and dynamic cloud of terms related to one or more input terms
Cable suspended chipper system
Flexible airflow baffle for an electronic system