Resources Contact Us Home
Address multiplex semiconductor memory device for enabling testing of the entire circuit or for only partial components thereof

Image Number 4 for United States Patent #5726994.

A memory array is logically and/or physically divided into a plurality of blocks to allow test by individual blocks. When a plurality of column address strobe signals are provided and memory accessing is made by a plurality of bits to the memory array corresponding to the column address strobe signal, tests are independently conducted for each memory array by using the column address strobe signal.

  Recently Added Patents
Solar cell with hyperpolarizable absorber
Emergent information database management system
Linear book scanner
Fabrication of high gradient insulators by stack compression
Modified and stabilized GDF propeptides and uses thereof
Systems and methods for switching supply load current estimation
Egg separator
  Randomly Featured Patents
Methods of characterizing ligands for the erbB-3 receptor, methods of influencing erbB-3 activities and methods of diagnosing erbB-3-related neoplasm
High strength and corrosion resistant aluminum article and method
Head model for representing gnathological relationships
Display driving apparatus and multi-line inversion driving method thereof
Coupling device for connection and disconnection of bottom-hole equipment
Method and system for determining tire pressure imbalances
Liquid crystal display panel and method for fabricating the same
Light-sensitive composition
Apparatus and method for trimming static delay of a synchronizing circuit
Gas collector electrode assembly