Resources Contact Us Home Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE     Address multiplex semiconductor memory device for enabling testing of the entire circuit or for only partial components thereof Image Number 4 for United States Patent #5726994. A memory array is logically and/or physically divided into a plurality of blocks to allow test by individual blocks. When a plurality of column address strobe signals are provided and memory accessing is made by a plurality of bits to the memory array corresponding to the column address strobe signal, tests are independently conducted for each memory array by using the column address strobe signal.       Recently Added Patents Disposable and tamper-resistant RFID lock Imidazo[1,2-B]pyridazine and pyrazolo[1 .5-A]pyrimidine derivatives and their use as protein kinase inhibitors Inkjet ink Personalized dashboard architecture for displaying data display applications Discharge lamp lighting circuit Coated article and method for making the same Systems and methods for processing telephone calls   Randomly Featured Patents Selectively reinforced member and method of manufacture VME slave tester Balustrade for a passenger conveyor Video signal processing system with a dynamic ADC calibration loop and related methods Laser catheter control and connecting apparatus Gas tap Neon sign Combined jar and seal or similar article System for generating a local electron-cyclotron microwave low-pressure plasma at a predetermined location within a processing chamber Charge retention structures and techniques for implementing charge controlled resistors in memory cells and arrays of memory © 2006-2008 PatentGenius. All Rights Reserved.