Resources Contact Us Home
Address multiplex semiconductor memory device for enabling testing of the entire circuit or for only partial components thereof

Image Number 10 for United States Patent #5726994.

A memory array is logically and/or physically divided into a plurality of blocks to allow test by individual blocks. When a plurality of column address strobe signals are provided and memory accessing is made by a plurality of bits to the memory array corresponding to the column address strobe signal, tests are independently conducted for each memory array by using the column address strobe signal.

  Recently Added Patents
Electrifying roller
Sonic fast-sync system and method for bluetooth
Representing polarized light in computer models
Antagonists of the glucagon receptor
Method and system for detecting target objects
Radiation detector array
Devices including composite thermal capacitors
  Randomly Featured Patents
Oil control valve assembly for engine cam switching
Method of determining maximum service brake reduction
Apparatus and method for dispensing disinfectant compositions for disinfecting water systems and lines
Torque sensor and electric steering device using the same
Latchable electrical connector system
Apparatus for repairing bone structure using laser
Lidded beach table with interior recessed cup holders
Square mandrel
Self positioning vacuum chuck
Mobile services