Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Address multiplex semiconductor memory device for enabling testing of the entire circuit or for only partial components thereof










Image Number 10 for United States Patent #5726994.

A memory array is logically and/or physically divided into a plurality of blocks to allow test by individual blocks. When a plurality of column address strobe signals are provided and memory accessing is made by a plurality of bits to the memory array corresponding to the column address strobe signal, tests are independently conducted for each memory array by using the column address strobe signal.








 
 
  Recently Added Patents
Timing and cell specific system information handling for handover in evolved UTRA
Wireless refrigerant scale platform
Computerized on-board system for controlling a train
Electrode tab for secondary battery and secondary battery using the same
Quantitative sleep analysis system and method
Display apparatus, a method for a display control, and program
Cooling method and device for cooling a medium-voltage electrical installation in a protective sheath
  Randomly Featured Patents
Utility suspenders
Photolytic iodine laser system with turbo-molecular blower
Out-of sector message stream delivery
System, method and media drive for selectively encrypting a data packet
Reproduction circuit for skin color in video signals
Metal wire chair
Ultrasonic surgical apparatus
Trailer assembly and method
Actuator with integrated equipment for condition monitoring and method for condition monitoring and method for producing an actuator
Ink-jet recording medium, method of manufacturing the same, and ink-jet recording apparatus using the same