Resources Contact Us Home
Address multiplex semiconductor memory device for enabling testing of the entire circuit or for only partial components thereof

Image Number 10 for United States Patent #5726994.

A memory array is logically and/or physically divided into a plurality of blocks to allow test by individual blocks. When a plurality of column address strobe signals are provided and memory accessing is made by a plurality of bits to the memory array corresponding to the column address strobe signal, tests are independently conducted for each memory array by using the column address strobe signal.

  Recently Added Patents
Optical packet signal transmission device and WDM optical communication network
Method and device for accessing the documentation of an aircraft according to alarms generated therein
System for targeted delivery of therapeutic agents
Process for preparing MDA via the stage of the aminal
Synchronization of communication equipment
Check weigher comprising of a rotating weighing chute with an accumulating and a discharge position that calculates flow rate by measuring weight accumulated during a predetermined time interv
  Randomly Featured Patents
Agricultural seeder
Legalization of VLSI circuit placement with blockages using hierarchical row slicing
Preparation of amorphous silica-alumina particles by acid-treating spherical P-type zeolite particles crystallized from a sodium aluminosilicate gel
Low shrink low density laminate formulation
Method of exercising on a stationary bicycle
Mobile terminal and broadcast controlling method thereof
Dimensionally stable high surface area anode comprising graphitic carbon fibers
Apparatus for forming fibers from attenuable material
Monitoring compaction of backfill