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Semiconductor memory device having a redundant memory cell

Image Number 17 for United States Patent #5706231.

NMOS transistors are arranged between bit lines included in a memory cell array and a node supplied with a power supply potential. The NMOS transistor corresponding to a defective column to be replaced with a redundant memory cell column is turned of in a standby mode. In the standby mode, therefore, it is possible to reduce a current flowing from a power supply for a power supply potential to a word line at a ground potential through the NMOS transistor, the bit line and a short-circuited portion between the bit line and the word line.

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