Resources Contact Us Home
Semiconductor memory device having a redundant memory cell

Image Number 14 for United States Patent #5706231.

NMOS transistors are arranged between bit lines included in a memory cell array and a node supplied with a power supply potential. The NMOS transistor corresponding to a defective column to be replaced with a redundant memory cell column is turned of in a standby mode. In the standby mode, therefore, it is possible to reduce a current flowing from a power supply for a power supply potential to a word line at a ground potential through the NMOS transistor, the bit line and a short-circuited portion between the bit line and the word line.

  Recently Added Patents
Non-intrusive processor tracing
Testing SQL query writing skills
Pyrazole kinase modulators and methods of use
Semiconductor overlapped PN structure and manufacturing method thereof
Air filter
Data consumption framework for semantic objects
Information processing apparatus, information outputting method and computer program storage device
  Randomly Featured Patents
Foot throttle for all-terrain vehicles
Method of measuring the angular position of the axis of rotation of a wheel
Data transfer method including recognizing identical messages and communication apparatus using the method
Electrical connector
High-frequency power amplifier module
Emulsification composition
Rehabilitation device for persons with paresis of lower limbs enabling them to walk
Chemically modified melamine resin for use in sublimation dye imaging
Filtration media
Sports equipment swing training apparatus and method of use