Resources Contact Us Home
Semiconductor memory device having a redundant memory cell

Image Number 13 for United States Patent #5706231.

NMOS transistors are arranged between bit lines included in a memory cell array and a node supplied with a power supply potential. The NMOS transistor corresponding to a defective column to be replaced with a redundant memory cell column is turned of in a standby mode. In the standby mode, therefore, it is possible to reduce a current flowing from a power supply for a power supply potential to a word line at a ground potential through the NMOS transistor, the bit line and a short-circuited portion between the bit line and the word line.

  Recently Added Patents
Generating agricultural information products using remote sensing
Method and apparatus for eliminating a motor vehicle tip-over risk
Imaging apparatus for calculating a histogram to adjust color balance
Segmentation of a product markup image based on color and color differences
Vehicle tail lamp
Field of view matching in a visual prosthesis
Image descriptor quantization
  Randomly Featured Patents
Cylinder block for an internal combustion engine having a locally thickened end wall
Method for measuring the quantity of a dried product
Email anti-phishing inspector
Crystal making method
Integrated circuit amplifier and method of adaptive offset
Data processor for concurrent executing of instructions by plural execution units
Fired refractory ceramic product
Method for protecting a computer from the manipulation of register contents and a corresponding computer for carrying out this method
Extended radio base station system having broadcast wave retransmitting function
Broadband RFI power line filter