Resources Contact Us Home
Semiconductor memory device having a redundant memory cell

Image Number 11 for United States Patent #5706231.

NMOS transistors are arranged between bit lines included in a memory cell array and a node supplied with a power supply potential. The NMOS transistor corresponding to a defective column to be replaced with a redundant memory cell column is turned of in a standby mode. In the standby mode, therefore, it is possible to reduce a current flowing from a power supply for a power supply potential to a word line at a ground potential through the NMOS transistor, the bit line and a short-circuited portion between the bit line and the word line.

  Recently Added Patents
Vehicle exterior
Wound dressings
Method and apparatus for automatically controlling gas pressure for a plasma cutter
Subscribing to content
Information processing apparatus and display control method
Use of physical deformation during scanning of an object to generate views of the object
  Randomly Featured Patents
System and method for providing interactive services using a mobile device
Molded electrical jack assembly
Ratchet wrench head with lubrication port
Ultra-violet filtration with certain aminosalicylic acid esters
Method and apparatus for facilitating reception of a signal on one of a plurality of contiguous channels
Interferon-gamma receptor fragment and its production
Golf training machine
Self light-emitting retroreflective sheet and method for producing the same
Extrusion die assembly