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Multi-processor resource locking mechanism with a lock register corresponding to each resource stored in common memory










Image Number 3 for United States Patent #5669002.

A method and apparatus to reduce bus usage and to increase resource locking protocol compatibility within a heterogeneous processing environment. Lock indicators are maintained in stores designated as lock registers and access to a resource is gained by any processor depending upon the status of a lock register associated with that resource. Access to a locked resource is barred to all but the locking processor, and only the processor which has set a lock can use or release that locked resource. A lock register controller controls the contents of the lock registers. A given processor P1-PN is identified by a unique ID vector G1-GN. These vectors are used to indicate both that a resource is locked and to indicate the identity of the locking processor. An unlocked resource is identified by a status vector (G.O slashed.). In a preferred embodiment, acquisition of exclusive access to an available resource is obtained with a simple read command; release of exclusive access is achieved with a simple write executed by the processor which has set the lock. By convention, processors will not access a resource requiring exclusive access until an inquiry of the associated lock register returns the G.O slashed. vector to the inquiring processor.








 
 
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