Resources Contact Us Home
High performance superscalar microprocessor including a dual-pathway circuit for converting cisc instructions to risc operations

Image Number 12 for United States Patent #5664136.

A superscalar microprocessor is provided which includes a integer functional unit and a floating point functional unit that share a high performance main data processing bus. The integer unit and the floating point unit also share a common reorder buffer, register file, branch prediction unit and load/store unit which all reside on the same main data processing bus. Instruction and data caches are coupled to a main memory via an internal address data bus which handles communications therebetween. An instruction decoder is coupled to the instruction cache and is capable of decoding multiple instructions per microprocessor cycle. Instructions are dispatched from the decoder in speculative order, issued out-of-order and completed out-of-order. Instructions are retired from the reorder buffer to the register file in-order. The functional units of the microprocessor desirably accommodate operands exhibiting multiple data widths. High performance and efficient use of the microprocessor die size are achieved by the sharing architecture of the disclosed superscalar microprocessor.

  Recently Added Patents
Method and apparatus for efficiently inserting fills in an integrated circuit layout
Blended block copolymer composition
Active constant power supply apparatus
Polycarbonate resin composition and formed product thereof
Dye sensitised solar cell
  Randomly Featured Patents
Apparatus for supporting and stabilizing an implement
Mobile automotive servicing apparatus
Semiconductor device including a chip having high-frequency circuit blocks
Inline coaxial balun-fed ultrawideband cornu flared horn antenna
Silica glass crucible and method for pulling up silicon single crystal using the same
Dirt cup latch mechanism for vacuum cleaner
Knowledge based spectrometer
Enhanced rake structure
Implementing programmable logic array embedded in mask-programmed ASIC
Tools and methods for programming an implantable valve