Resources Contact Us Home
Clock recovery circuit of demodulator

Image Number 15 for United States Patent #5651031.

A clock recovery circuit capable of outputting decision point data without causing any slip of a recovered clock in the case of operation in a continuous mode in a demodulator in which received signals are sampled by a fixed frequency clock to obtain the recovered clock and symbol data are demodulated by using this recovered clock. A shift register stores digital received signals obtained by an A/D conversion of quasi-coherent detection received signals, and a clock phase estimator calculates an estimated phase difference between an output value of a phase generator operated by the fixed frequency clock and a symbol clock of the received signals and outputs timing information and phase information of a decision point for discriminating the data of the received signals. An interpolator inputs the output signal of the clock phase estimator, takes in the digital received signals from the shift register and calculates decision point data by interpolation to output the same. The interpolator operates at the same cycle as the symbol clock on an average.

  Recently Added Patents
Case for electronic device
Peer-to-peer method of deploying and managing executable code and associated plug-ins
Method of creating exercise routes for a user and related personal navigation device
Method for generating multi-antenna signals
Apparatus and method for sterilizing vessel with electron beam
Pattern forming method using printing device and method of manufacturing liquid crystal display device using the same
Nacelle cover
  Randomly Featured Patents
Pick-up device
Electromagnetically-controlled flat knitting machine
Means for the sealing of a toner cartridge
Automating emergency calls globally
Brushless DC motor for fuel pump
Mobile calf care station
Display panel structure and manufacture method thereof
Image processing method and apparatus
Disk array device with selectable method for generating redundant data