Resources Contact Us Home
Postage metering system

Image Number 18 for United States Patent #5602742.

A postage management system is disclosed that enables the use of one of a plurality of carriers from any station in the network. The system imprints postage on postal and private courier parcels and envelopes. Each station of the system has a central processing unit (CPU), an operating system, and a user communications link with the CPU having an embedded software program therewithin. The software program has a permanent portion and a configurable portion, and the configurable portion, in turn, has a postage rate database, a postage service database, and a management program. The databases include on a carrier-by-carrier basis the postal costs for parcels and envelopes of various configurations and specifications for a various parcel and envelope configurations, respectively. The system software includes both user and system default parameter schemes enabling a user to predetermine common patterns of use and quickly employ a given modality. The permanent portion of the embedded software has a rate comparator program which operates with the management program to provide optimization of services.

  Recently Added Patents
System and method for detecting deadlock in a multithread program
Satellite mounting poles
Indicating transfer in an IMS network
Semiconductor device having germanium active layer with underlying parasitic leakage barrier layer
Semiconductor memory device
Front face of a vehicle wheel
  Randomly Featured Patents
Disk-type faucet
Belleville spring
Range switchover apparatus for automatic transmission
Substituted anthranilic acids, their use as a medicament or diagnostic, and medicament comprising them, and a pharmaceutical combination preparation containing a sodium/hydrogen exchange (NHE)
Shoe cleaning doormat device
Control circuit for an ultrasonic dental scaler
Portion of step ladder
Apparatus and method of boring using laser
One-piece glass prefilled syringe system
Method and structure for reading, modifying and writing selected configuration memory cells of an FPGA