Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Hierarchical cache system flushing scheme based on monitoring and decoding processor bus cycles for flush/clear sequence control










Image Number 4 for United States Patent #5581727.

An apparatus for monitoring and decoding processor bus cycles and flushing a second level cache upon decoding a special flush acknowledge cycle. The CPU preferably includes an internal cache and a flush input for receiving a signal commanding the CPU to flush its internal cache. After flushing its cache by performing any necessary cycles to write back dirty data to main memory, the CPU performs a special flush acknowledge cycle to inform external devices that the flush procedure has been completed. A cache controller detects the flush acknowledge cycle and provides a flush signal to the second level cache. The cache controller then provides an end of cycle signal to the CPU to indicate that the flush cycle has been acknowledged.








 
 
  Recently Added Patents
Synchronization scheduling apparatus and method in real-time multi-core system
Image forming apparatus forming images in response to image formation request from operation unit or external device
Dynamic bar oriented user interface
Indexing, relating and managing information about entities
Vacuum cleaner
Snapshots in de-duplication
Methods and apparatus for imaging in conjunction with radiotherapy
  Randomly Featured Patents
Peach tree (7-7-52)
CD storage tower with central storage unit
High current fast rise and fall time LED driver
Apparatus and method for manufacturing gas-filled balls with precision
Method and system for processing aquatic plants
Amine derivatives for treatment of skin disorders
Method of producing insulated gate MOSFET employing polysilicon mask
Ink cartridge
Dihydrotriazinylthiooxacephalosporins
Oil soluble coking additive, and method for making and using same