Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Hierarchical cache system flushing scheme based on monitoring and decoding processor bus cycles for flush/clear sequence control










Image Number 4 for United States Patent #5581727.

An apparatus for monitoring and decoding processor bus cycles and flushing a second level cache upon decoding a special flush acknowledge cycle. The CPU preferably includes an internal cache and a flush input for receiving a signal commanding the CPU to flush its internal cache. After flushing its cache by performing any necessary cycles to write back dirty data to main memory, the CPU performs a special flush acknowledge cycle to inform external devices that the flush procedure has been completed. A cache controller detects the flush acknowledge cycle and provides a flush signal to the second level cache. The cache controller then provides an end of cycle signal to the CPU to indicate that the flush cycle has been acknowledged.








 
 
  Recently Added Patents
Method and apparatus for managing communication services for user endpoint devices
Viewing stand
Method and device for managing subscriber connection
Method and apparatus for sensing an input object relative to a sensing region of an ultrasound sensor device
Volume compensation within a photovoltaic device
Radiation imaging device
Method for automatically estimating inertia in a mechanical system
  Randomly Featured Patents
Plastic reclamation process
High efficiency binary encoding
Portable device for use in playing step-ball
Ratcheting apparatus for cargo strap winches
Modulator for modulating digital signals
Process for producing caprolactam
Operator control system for an automobile
Continuous process for producing a silicone polymer
Calibration of pulse transit time measurements to arterial blood pressure using external arterial pressure applied along the pulse transit path
Chair with animal design back