Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Hierarchical cache system flushing scheme based on monitoring and decoding processor bus cycles for flush/clear sequence control










Image Number 4 for United States Patent #5581727.

An apparatus for monitoring and decoding processor bus cycles and flushing a second level cache upon decoding a special flush acknowledge cycle. The CPU preferably includes an internal cache and a flush input for receiving a signal commanding the CPU to flush its internal cache. After flushing its cache by performing any necessary cycles to write back dirty data to main memory, the CPU performs a special flush acknowledge cycle to inform external devices that the flush procedure has been completed. A cache controller detects the flush acknowledge cycle and provides a flush signal to the second level cache. The cache controller then provides an end of cycle signal to the CPU to indicate that the flush cycle has been acknowledged.








 
 
  Recently Added Patents
Motion control system and X-ray measurement apparatus
Intelligent sensor network
Identification of biomarkers in biological samples and methods of using same
Modification of an object replica
Adaptive frame scanning scheme for pulsed X-ray imaging
Tools and methods for yield-aware semiconductor manufacturing process target generation
Peer-to-peer, internet protocol telephone system with proxy interface for configuration data
  Randomly Featured Patents
Noise and quality detector for use with turbo coded signals
Monitor circuit for extracting administration information in a communication frame
Piston for internal combustion engine
Method and system for balancing component load in an input/output stack of an operating system
Composite beam structure
Control of active power reserve in a wind-farm
Composite electronic component and frequency adjustment method of the same
Etchant and method of manufacturing an array substrate using the same
Method for testing electrical loads in a vehicle electrical system
Data processing system and method for maintaining translation lookaside buffer TLB coherency without enforcing complete instruction serialization