Resources Contact Us Home
Hierarchical cache system flushing scheme based on monitoring and decoding processor bus cycles for flush/clear sequence control

Image Number 4 for United States Patent #5581727.

An apparatus for monitoring and decoding processor bus cycles and flushing a second level cache upon decoding a special flush acknowledge cycle. The CPU preferably includes an internal cache and a flush input for receiving a signal commanding the CPU to flush its internal cache. After flushing its cache by performing any necessary cycles to write back dirty data to main memory, the CPU performs a special flush acknowledge cycle to inform external devices that the flush procedure has been completed. A cache controller detects the flush acknowledge cycle and provides a flush signal to the second level cache. The cache controller then provides an end of cycle signal to the CPU to indicate that the flush cycle has been acknowledged.

  Recently Added Patents
Method and apparatus for increasing query traffic to a web site
Communication apparatus and communication system
Information processing apparatus capable of authentication processing with improved user convenience, control program for information processing apparatus, and recording medium having control
Documentation roadmaps and community networking for developers on large projects
High performance adaptive switched LED driver
Touchscreen with Z-velocity enhancement
  Randomly Featured Patents
Method and apparatus for arbitrating access
Vertebral anchoring methods
Kaolinite aggregation using organo-silicon compounds
Decorative strip for showers
Dielectric element including oxide-based dielectric film and method of fabricating the same
Method and apparatus for drying web
Portable vacuum object handling device
Mechanism for dynamically associating a service dependent representation with objects at run time
Drilling mud cleaning system
Apparatus for recovering and saving chilled water in hot water lines having adjustable thermostatic control