Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Hierarchical cache system flushing scheme based on monitoring and decoding processor bus cycles for flush/clear sequence control










Image Number 4 for United States Patent #5581727.

An apparatus for monitoring and decoding processor bus cycles and flushing a second level cache upon decoding a special flush acknowledge cycle. The CPU preferably includes an internal cache and a flush input for receiving a signal commanding the CPU to flush its internal cache. After flushing its cache by performing any necessary cycles to write back dirty data to main memory, the CPU performs a special flush acknowledge cycle to inform external devices that the flush procedure has been completed. A cache controller detects the flush acknowledge cycle and provides a flush signal to the second level cache. The cache controller then provides an end of cycle signal to the CPU to indicate that the flush cycle has been acknowledged.








 
 
  Recently Added Patents
Information processing using batch setting information
Semiconductor device
Method and CTDevice for computer tomographic spiral scanning of a patient
Methods and apparatus for voltage selection for a MOSFET switch device
Lighting fixture
Hemostatic devices and methods of making same
Notification systems and methods that consider traffic flow predicament data
  Randomly Featured Patents
Alignment of fiber optic bundle to array waveguide using pins
Stable polysulfides and process therefor
Blown microfiber insulated cable
Recording material separating apparatus of which separating member is retractable in operative association with guide
Hot melt adhesive composition
Uniaxial tension focus mask for color CRT and method of making same
Pharmaceutical composition
Multi-purpose container handling device
Rolling piston rotary compressor formed with lubrication grooves
System for accumulating exposure energy information of wafer and management method of mask for exposure utilizing exposure energy information of wafer accumulated with the system