Resources Contact Us Home
Hierarchical cache system flushing scheme based on monitoring and decoding processor bus cycles for flush/clear sequence control

Image Number 4 for United States Patent #5581727.

An apparatus for monitoring and decoding processor bus cycles and flushing a second level cache upon decoding a special flush acknowledge cycle. The CPU preferably includes an internal cache and a flush input for receiving a signal commanding the CPU to flush its internal cache. After flushing its cache by performing any necessary cycles to write back dirty data to main memory, the CPU performs a special flush acknowledge cycle to inform external devices that the flush procedure has been completed. A cache controller detects the flush acknowledge cycle and provides a flush signal to the second level cache. The cache controller then provides an end of cycle signal to the CPU to indicate that the flush cycle has been acknowledged.

  Recently Added Patents
Packet transmission method, apparatus, and network system
Sensor chip, sensor cartridge, and analysis apparatus
Systems and methods for classifying electronic information using advanced active learning techniques
Paper product with surface pattern
Method of forming a power supply controller and structure therefor
System and method for updating firmware
  Randomly Featured Patents
Oscillator system, method of providing a resonating signal and a communications system employing the same
Overmolded frame bus with integral pressure switch
Spreading apparatus for sheet feeder
Crib safety sheet/blanket
Hydroprocessing catalyst and its use
Heated hand grips
Separating compositions
Memory access control device, integrated circuit, memory access control method, and data processing device
Dimmer switch
Apparatus for optically reading signal information recorded on a reflective record medium surface