Resources Contact Us Home
Reducing the natural current limit in a power MOS device by reducing the gate-source voltage

Image Number 3 for United States Patent #5541799.

In accordance with the present invention, an output current limit circuit for protecting a power MOS output device of an integrated circuit from an excessive drain current comprises a power MOS device 110, a means 30 to sense a predetermined trigger current, and a means 20 to reduce a gate-source voltage on MOS output device 110 to a predetermined approximately fixed value. A drain current I.sub.D flows through power MOS device 110 from output terminal 102 in response to the gate-source voltage. A short circuit condition may allow an excessive amount of drain current I.sub.D to flow through output terminal 102. The gate-source voltage is reduced in response to sensing the trigger current. Reducing the gate-source voltage raises a drain-source resistance of MOS device 110 and reduces drain current I.sub.D so that MOS device 110 is not damaged by the short circuit condition.

  Recently Added Patents
Extensible framework for client-based active network measurement
Inductive antenna coupling
Regulating a supply voltage provided to a load circuit
Salts and polymorphs of desazadesferrithiocin polyether analogues as metal chelation agents
Method for fabricating a nitrided silicon-oxide gate dielectric
Method for producing vinyl acetate monomer
Managing job execution
  Randomly Featured Patents
Combined set of canisters and display holder therefor
Immunoassay with antigen or antibody labelled microcapsules containing fluorescent substance
Multi-cylinder internal combustion engine
Mobile telephone with improved man machine interface
High speed low voltage driver
Image forming system and optical screen unit
Food wrapper for a dried seaweed covered mass of rice
Fluidically mounted apparatus for measuring the torque in a shaft
Repetitive controller to compensate for odd harmonics
Cell selection in a mobile communication method and radio base station