Resources Contact Us Home
Reducing the natural current limit in a power MOS device by reducing the gate-source voltage

Image Number 3 for United States Patent #5541799.

In accordance with the present invention, an output current limit circuit for protecting a power MOS output device of an integrated circuit from an excessive drain current comprises a power MOS device 110, a means 30 to sense a predetermined trigger current, and a means 20 to reduce a gate-source voltage on MOS output device 110 to a predetermined approximately fixed value. A drain current I.sub.D flows through power MOS device 110 from output terminal 102 in response to the gate-source voltage. A short circuit condition may allow an excessive amount of drain current I.sub.D to flow through output terminal 102. The gate-source voltage is reduced in response to sensing the trigger current. Reducing the gate-source voltage raises a drain-source resistance of MOS device 110 and reduces drain current I.sub.D so that MOS device 110 is not damaged by the short circuit condition.

  Recently Added Patents
Plants and seeds of hybrid corn variety CH979678
Control device
System for non-destructive image processing
Multilayer films having reduced curling
Pixel circuit
Systems and methods for dynamically modifying subcriber service profile stored in home location register while roaming in wireless telecommunication networks
  Randomly Featured Patents
Foam modifier, foams prepared from this novel foam modifier and a process for the preparation of these foams
Novel alkanephosphonic monoester salts, preparation thereof and use thereof as spin finishes for textile fibers
Amusement and educational game
Instant, accurate, and efficient product recommendations to client endpoint
Apparatus and method of detecting error symbol, and disk drive apparatus using the same
Work cart
Drapery pleating guide for sewing machines
Business hour notification delivery
Expansible device
Valve assembly for use in a wellbore