Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Reducing the natural current limit in a power MOS device by reducing the gate-source voltage










Image Number 3 for United States Patent #5541799.

In accordance with the present invention, an output current limit circuit for protecting a power MOS output device of an integrated circuit from an excessive drain current comprises a power MOS device 110, a means 30 to sense a predetermined trigger current, and a means 20 to reduce a gate-source voltage on MOS output device 110 to a predetermined approximately fixed value. A drain current I.sub.D flows through power MOS device 110 from output terminal 102 in response to the gate-source voltage. A short circuit condition may allow an excessive amount of drain current I.sub.D to flow through output terminal 102. The gate-source voltage is reduced in response to sensing the trigger current. Reducing the gate-source voltage raises a drain-source resistance of MOS device 110 and reduces drain current I.sub.D so that MOS device 110 is not damaged by the short circuit condition.








 
 
  Recently Added Patents
Base station apparatus and communication control method
System and method for routing streaming data requests
Hand-held electronic display device
Level-shift circuit, electro-optical device, and level shift method
Semiconductor chip, stack module, and memory card
(4932
Image forming apparatus and method for making density correction in a low resolution image based on edge determination
  Randomly Featured Patents
Supports for silver catalysts utilized in the production of ethylene oxide
Porose, pulverformige polymerteilchen
Amphibian motor vehicle
Inhibitor of tissue factor activity
Audio amplifier
Horizontal twin wire machine
Foam roller
Disposable sitz bath
Electronic control sensor systems
Nucleic acids encoding novel chimeric C15/prM/E dengue virus immunogens prepared by DNA shuffling