Resources Contact Us Home
Semiconductor memory device having an SRAM as a cache memory integrated on the same chip and operating method thereof

Image Number 3 for United States Patent #5509132.

A cache DRAM (100) includes a DRAM memory array (11) accessed by a row address signal and a column address signal, an SRAM memory array (21) accessed by the column address signal, and an ECC circuit (30). The DRAM memory array (11) is divided into a plurality of blocks (B1 to B64), each including a plurality of columns. The SRAM memory array (21) includes 4 ways (W1 to W4). In determining a cache hit/cache miss, a column address signal is inputted. Consequently, the SRAM memory array (21) is accessed and data are read from each of the ways. When a cache hit occurs, one way is selected in response to an externally applied way address signal, and data from that way are outputted. When a cache miss occurs, the column address signal is latched and the row address signal is applied. The DRAM array (11) is accessed in accordance with the row address signal and the latched column address signal.

  Recently Added Patents
Voltage detecting device for LED driver
Method of treating lung cancer
Liquid crystal display device
Pet carrier
Process to extract quassinoids
Systems and methods for selective text to speech synthesis
Storage device, data processing device, registration method, and recording medium
  Randomly Featured Patents
Field effect transistors having multiple stacked channels
Catalyst for curing resins
Axle axial motion limiting device for a rotating component shaft position adjustment
Method and system for processing communications orders
Business form with wristband carriers
MOS memory cell with exponentially-profiled doping and offset floating gate tunnel oxidation
Portable battery charger
Application software add-on for enhanced internet based marketing
1,4,5-triphenylimidazol-2-yl mercapto alkanoic acids, useful against inflammation and diseases responding to lipid lowering
Petunia plant named `Hoobenihime`