Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Concurrent simulation of host system at instruction level and input/output system at logic level with two-way communication deadlock resolution










Image Number 2 for United States Patent #5493672.

A method and apparatus is provided for integrating a logic level simulation with an instruction level simulation for more accurate and faster system level simulation for testing. A host system or processors (CPU) is simulated by the instruction level simulator and the simulation of an input/output subsystem is modeled by the logic level simulator. The two simulations work side by side communicating through an interprocess communication (IPC) device and both simulations can perform a read/write access. Hence, a DMA and a slave access can occur at the same time causing a deadlock situation where both simulators are waiting for data and acknowledgment from each other at the same time. An input/output subsystem SBus module resolves this deadlock by deferring the non-DMA transaction. Finally, the synchronization of the two simulations is handled by the invention allowing the two simulators to run as asynchronous peers.








 
 
  Recently Added Patents
Deceleration dependent shift control
Authentication method
Image forming apparatus to automatically select a communication condition
Anthranilic diamide compositions for propagle coating
Wire guide
Method and apparatus for providing seamless call handoff between networks that use dissimilar transmission methods
Biological information monitoring system
  Randomly Featured Patents
Helicoidal propeller pitch control mechanism
Projectile propelling attachment for toy figures
Fully integrated micro-strip VCO
Method for manufacturing thin film transistor, electro-optical device, and electronic apparatus
Semiconductor device and semiconductor storage device
Image correction system and method
Finger ring
Fuel/air mixing using swirl chamber
Process for making high-active detergent agglomerates by multi-stage surfactant paste injection
Methods to assay for post-transcriptional suppression of gene expression