Resources Contact Us Home
Concurrent simulation of host system at instruction level and input/output system at logic level with two-way communication deadlock resolution

Image Number 2 for United States Patent #5493672.

A method and apparatus is provided for integrating a logic level simulation with an instruction level simulation for more accurate and faster system level simulation for testing. A host system or processors (CPU) is simulated by the instruction level simulator and the simulation of an input/output subsystem is modeled by the logic level simulator. The two simulations work side by side communicating through an interprocess communication (IPC) device and both simulations can perform a read/write access. Hence, a DMA and a slave access can occur at the same time causing a deadlock situation where both simulators are waiting for data and acknowledgment from each other at the same time. An input/output subsystem SBus module resolves this deadlock by deferring the non-DMA transaction. Finally, the synchronization of the two simulations is handled by the invention allowing the two simulators to run as asynchronous peers.

  Recently Added Patents
Process for producing a plasma protein-containing medicament with reduced concentration of citrate and metals
Real ear measurement system using thin tube
Apparatus and method for transmitting/receiving data in a communication system
Communication apparatus, communication method, and communication system
Process for preparing soybean curd using micronized solution of soybean curd
Tone enhancement bracket
Porous objects having immobilized encapsulated biomolecules
  Randomly Featured Patents
Veneer slicer
Adjustable rebound stop for axle/suspension systems
Niobium powder, sintered body thereof, and capacitor using the same
Polarizing beamsplitter
Conveyor assembly for providing selectively spaced products
Electric terminal
Jacketed axial magnetic bearing
Electronic spatial logical toy containing movable and/or rotatable elements
Peanut combine
Fabrication of semiconductor structure in which complementary field-effect transistors each have hypoabrupt body dopant distribution below at least one source/drain zone