Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Concurrent simulation of host system at instruction level and input/output system at logic level with two-way communication deadlock resolution










Image Number 2 for United States Patent #5493672.

A method and apparatus is provided for integrating a logic level simulation with an instruction level simulation for more accurate and faster system level simulation for testing. A host system or processors (CPU) is simulated by the instruction level simulator and the simulation of an input/output subsystem is modeled by the logic level simulator. The two simulations work side by side communicating through an interprocess communication (IPC) device and both simulations can perform a read/write access. Hence, a DMA and a slave access can occur at the same time causing a deadlock situation where both simulators are waiting for data and acknowledgment from each other at the same time. An input/output subsystem SBus module resolves this deadlock by deferring the non-DMA transaction. Finally, the synchronization of the two simulations is handled by the invention allowing the two simulators to run as asynchronous peers.








 
 
  Recently Added Patents
Communications in an asynchronous cellular wireless network
Comb
Surface emitting laser device, surface emitting laser array, optical scanning device, and image forming apparatus
Wearable display device
Measurement system service for a vehicle instrument panel
Disposable and tamper-resistant RFID lock
Cartridge for conducting a chemical reaction
  Randomly Featured Patents
Hepadnavirus receptor
Method for purifying acrylic acid obtained by oxidation of propylene and/or acrolein
Imaging member
Single cell and stack structure for solid oxide fuel cell stacks
Handle
Side impact load transmitting structure
Print head and image formation apparatus
Aerial work assembly using composite materials
Gate assembly and method of use thereof
Multi-purpose utensil for food preparation