Image Number 3 for United States Patent #5452183.
This invention is directed to a chip carrier system for mounting to a first planar electronic device, such as a motherboard or test fixture, where first planar electronic device is provided with a planar, electrical interconnection interface mounted thereto. The chip carrier system includes a frame comprising a peripheral body portion defined by upper and lower planar surfaces, a recess in the lower planar surface to receive the planar, electrical interconnection interface, a central recess terminating in a floor to receive a second planar electronic device, such as an integrated circuit chip, having leads extending therefrom, converging side walls extending from the upper planar surface down to the floor, and plural through slots for receiving the leads. Cooperating therewith is a force applying member adapted to provide a normal force to the second planar electronic device and be mechanically secured to the frame. The force applying member includes plural ribs arranged to overlie portions of the converging side walls, whereby as the force applying member is brought into engagement with the frame, the ribs, in contact with the converging side walls, are cammed inwardly into contact with the leads of the second planar electronic device to apply a normal force thereto in contact with a resilient electrical connector associated with the planar, electrical interconnection interface.