Image Number 2 for United States Patent #5440546.
The present invention pertains to a packet switch. The packet switch is comprised of a global shared-memory queue having M storage addresses in which respective packets are stored, where M.gtoreq.3 and is an integer. The packet switch is also comprised of a presentation network having N input ports for receiving packets and providing the respective packets to desired addresses in the queue, where N.ltoreq.3 and is an integer. The queue is in communication with the presentation network for receiving the packets. The packet switch is also comprised of a distribution network having J input ports, where J.ltoreq.1, for receiving packets from the queue and providing them to the desired output ports. The distribution network is in communication with the queue. There is also means for ordering packets received by the presentation network such that packets received sequentially by the presentation network are caused to be provided by the presentation network to consecutive addresses in the queue. In a preferred embodiment, M=N=J, the ordering means includes a fetch-and-add circuit in communication with the queue such that it identifies addresses free for storage of packets being received by the presentation switch, and causes the packets being received by the presentation network to be placed into consecutive addresses free for storage; and the presentation network and the distribution network are each a .OMEGA. switch. In an even more preferred embodiment, the packet switch has multicast capability.