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Twin tub CMOS process

Image Number 5 for United States Patent #5413944.

A method of manufacturing a twin-tub structure for a CMOS (Complementary Metal Oxide Semicondcuctor) device is described. A first conductivity-imparting dopant is implanted in a silicon substrate. A photoresist layer is formed over a portion of the silicon substrate, to act as a mask. A portion of the top surface of the silicon substrate is removed in the region not masked by the photoresist layer. A second conductivity-imparting dopant, of an opposite type to the first conductivity-imparting dopant, is implanted into the region of the silicon substrate not masked by the photoresist layer. The photoresist layer is removed. A first insulating layer is formed over the silicon substrate. A second insulating layer is formed over the first insulating layer. The second insulating layer is patterned to form an active region mask centrally located over the planned location of each tub of the twin tub structure. Tubs are formed in the silicon substrate. Field oxide regions are formed in and on the surface of the silicon substrate, between the active region masks. The remainder of the second insulating layer is removed. A third conductivity-imparting dopant, of the same type as the second conductivity-imparting dopant, is implanted into the same region as the second conductivity-imparting dopant.

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