Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Method for sizing widths of power busses in integrated circuits










Image Number 7 for United States Patent #5349542.

Segments within a power network of an integrated circuit are calculated utilizing information generated during design and placement. The performance of logic blocks within the integrated circuit is simulated to obtain an estimated maximum current requirement for each logic block. After obtaining an estimated maximum current requirement for each logic block, the estimated maximum current flow through each power net segment is obtained by summing the estimated current requirements for each logic block which draws current through the power net segment. Based on this estimated maximum current flow through each power segment, a width for each power net segment is calculated. After widths have been calculated, a check may be made to assure that a predetermined electromigration limit is not exceeded. When projected current flow through a power net segment will result in an exceeding of the predetermined electromigration limit, the width of the power net segment is increased.








 
 
  Recently Added Patents
Electronic package with fluid flow barriers
Fused thiazole derivatives as kinase inhibitors
Jet pump and reactor
Determination and presentation of package pricing offers in response to customer interest in a product
Code reading apparatus, sales registering apparatus, and sales registering method
Faucet
Method for automatically estimating inertia in a mechanical system
  Randomly Featured Patents
Dental laser brushing or cleaning device
Antibodies and related molecules that bind to PSCA proteins
Apparatus for regulating feed thickness in a belt press
Method for producing optically active amino acid derivative
Wayfinding system
Cabinet for cut off flowers
Surgical sensor
Preparation of glycidyl esters of unsaturated acids
Copolymerized polyamide and a production process/thereof
Device for cutting pipes