Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Method for sizing widths of power busses in integrated circuits










Image Number 3 for United States Patent #5349542.

Segments within a power network of an integrated circuit are calculated utilizing information generated during design and placement. The performance of logic blocks within the integrated circuit is simulated to obtain an estimated maximum current requirement for each logic block. After obtaining an estimated maximum current requirement for each logic block, the estimated maximum current flow through each power net segment is obtained by summing the estimated current requirements for each logic block which draws current through the power net segment. Based on this estimated maximum current flow through each power segment, a width for each power net segment is calculated. After widths have been calculated, a check may be made to assure that a predetermined electromigration limit is not exceeded. When projected current flow through a power net segment will result in an exceeding of the predetermined electromigration limit, the width of the power net segment is increased.








 
 
  Recently Added Patents
Subscribing to content
Process for the enzymatic reduction of enoates
HYR1 as a target for active and passive immunization against Candida
Method and device for evaluating evolution of tumoural lesions
Secure provisioning of a portable device using a representation of a key
In-store marketing sign
Display unit and display method
  Randomly Featured Patents
Porous electrode, and electrochemical element made using the same
Rake trolley with adjustable working widths suitable for finger wheel hay rakes
Flowering crab apple tree `Sinai Fire`
RNAi modulation of RSV and therapeutic uses thereof
Energy distribution and communication system and method utilizing a communication message frame for a multi-device vehicle occupant protection system
Low alloy cold-worked martensitic steel
Flexible gas tight electrical connection for generators
Method of making titanium disulfide
CMOS-TFT Array substrate and method for fabricating the same
Method of induction bonding juxtaposed structural members