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Self arc-extinguishing thyristor and method of manufacturing the same

Image Number 14 for United States Patent #5345095.

A self arc-extinguishing thyristor having a large main current is disclosed. An n-type base layer is formed on a p-type anode layer. The n-type base layer includes in its top center portion a relatively heavily doped p+-type region which is surrounded by p-type region. A p-type base layer is locally coated at its top surface with a relatively thin first n-type emitter layer and a relatively thick second n-type emitter layer. A gate electrode buried in a gate oxide film is disposed on two channel regions and areas around the same. This structure suppresses a current amplification factor of a parasitic thyristor which is formed by the n-type base layer, the p-type region and the first n-type emitter layer, which in turn represses latching up of the parasitic thyristor.

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