Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Integrated circuit memory with dual P-sense amplifiers associated with each column line










Image Number 4 for United States Patent #5323350.

A DRAM or VRAM integrated circuit memory of the divided bit line design includes a bit line pair extending from a column decoder to a SAM. An N-sense amplifier divides the bit line pair into two pairs of bit halves. The N-sense amplifier is connected to each of the bit line halves through an isolation transistor. A P-sense amplifier is connected across each pair of the bit line halves. Since a P-sense amplifier is associated with each pair of bit line halves, the P-sense amplifier never has to pull through isolation transistors, and thus the isolation transistors can be high threshold transistors, eliminating the natural threshold mask step in fabrication. The two P-sense amplifiers separate the bit line voltages faster, thereby decreasing crossing current and saving power, and pull the bit lines to full high voltage levels.








 
 
  Recently Added Patents
Oxidative coupling of hydrocarbons as heat source
Semiconductor device with an amorphous semi-insulating layer, temperature sensor, and method of manufacturing a semiconductor device
Combination immunotherapy for the treatment of cancer
Triazole derivatives as ghrelin analogue ligands of growth hormone secretagogue receptors
Techniques for accessing a parallel database system via external programs using vertical and/or horizontal partitioning
Methods and arrangements for realising betting with off-line terminal
Liquid crystal display
  Randomly Featured Patents
Latching sense amplifier structure with pre-amplifier
Simultaneous multibeam scanning system
Adjustable positioning mechanism
Backlight module
Barbecue grill assembly
System, method, and network elements for providing a service such as an advice of charge supplementary service in a communication network
Filter element with percussion band
Dry cleaning still apparatus
Method and circuitry for enabling and permanently disabling test mode access in a flash memory device
CSP Semiconductor device having signal and radiation bump groups