Resources Contact Us Home
Stacked chip assembly and manufacturing method therefor

Image Number 3 for United States Patent #5311401.

Two or more integrated circuit or memory chips (64-66, 104, 106-108, 116-118, 122-126) are stacked on a circuit substrate (72, 100) or a printed-wiring board in such a manner that the planes of the chips lie horizontally, rather than vertically, on the substrate or wiring board. The chips are preferably interconnected along all of their edges (68) and thence, preferably by ribbon bonds, to the substrate or wiring board. The thus assembled arrangement is hermetically sealed by coatings of passivation and encapsulant. Such chips (25) are oversized, as distinguished from chips conventionally diced from wafers. Specifically, each chip is larger than an individual wafer circuit (18, 20), that is, each wafer portion (24) which is selected to be formed into a chip has a size that is larger than the individual wafer circuit which it incorporates, thus overlapping adjacent circuits.

  Recently Added Patents
Communication apparatus, communication method, and communication system
Apparatus, system, and method for non-interruptively updating firmware on a redundant hardware controller
Image processing apparatus and image processing method
Systems and methods for unchoked control of gas turbine fuel gas control valves
Terminal device and image printing method
Driver circuit for driving semiconductor switches
Method and apparatus for networked modems
  Randomly Featured Patents
Video time-shifting apparatus
Special item holder for label-holding data strip
Route search device and route search method
Process for controlling eradicating or preventing infestations of animals by Ixodid ticks
Lens protection structure for miniature lens focusing mechanism
Adjustable volume setting mechanism for repeatable fluid discharge device
Electronic smoking article
Method and apparatus for providing insurance policies for gambling losses
Circuit for detecting relative angular displacement of a steering wheel
Maximum likelihood sequence estimator which computes branch metrics in real time