Resources Contact Us Home
Stacked chip assembly and manufacturing method therefor

Image Number 3 for United States Patent #5311401.

Two or more integrated circuit or memory chips (64-66, 104, 106-108, 116-118, 122-126) are stacked on a circuit substrate (72, 100) or a printed-wiring board in such a manner that the planes of the chips lie horizontally, rather than vertically, on the substrate or wiring board. The chips are preferably interconnected along all of their edges (68) and thence, preferably by ribbon bonds, to the substrate or wiring board. The thus assembled arrangement is hermetically sealed by coatings of passivation and encapsulant. Such chips (25) are oversized, as distinguished from chips conventionally diced from wafers. Specifically, each chip is larger than an individual wafer circuit (18, 20), that is, each wafer portion (24) which is selected to be formed into a chip has a size that is larger than the individual wafer circuit which it incorporates, thus overlapping adjacent circuits.

  Recently Added Patents
Self-assembling surface coating
Signal activated molecular delivery
Optical multiplexer/demultiplexer
Shoe upper
System and method for testing an integrated circuit embedded in a system on a chip
Multi-carrier operation for wireless systems
Method of and apparatus for evaluating an optimal irradiation amount of an electron beam for drawing a pattern onto a sample
  Randomly Featured Patents
Internal combustion engine having combustion heater
High speed intelligent cable
PE/PP bag weaving machine without a power lubrication and cooling system
Faucet spout
Cosmetic temporary coloring compositions containing protein derivatives
Combined audio and video amplifier
System for regulating the fuel supply of an internal combustion engine
Liquid crystal display with corrugated reflective surface
Merge and split fast hartley block transform method
Single-lens reflex camera with built-in flash