Resources Contact Us Home
Stacked chip assembly and manufacturing method therefor

Image Number 3 for United States Patent #5311401.

Two or more integrated circuit or memory chips (64-66, 104, 106-108, 116-118, 122-126) are stacked on a circuit substrate (72, 100) or a printed-wiring board in such a manner that the planes of the chips lie horizontally, rather than vertically, on the substrate or wiring board. The chips are preferably interconnected along all of their edges (68) and thence, preferably by ribbon bonds, to the substrate or wiring board. The thus assembled arrangement is hermetically sealed by coatings of passivation and encapsulant. Such chips (25) are oversized, as distinguished from chips conventionally diced from wafers. Specifically, each chip is larger than an individual wafer circuit (18, 20), that is, each wafer portion (24) which is selected to be formed into a chip has a size that is larger than the individual wafer circuit which it incorporates, thus overlapping adjacent circuits.

  Recently Added Patents
Novelty headband
Dual source mass spectrometry system
Methods and devices for enforcing network access control utilizing secure packet tagging
Device for data routing in networks
Image scanning apparatus and image forming apparatus
Emergent information database management system
  Randomly Featured Patents
Method and system for identifying job candidates
Wave-powered pneumatic system for power generation
Method and apparatus for measuring concentration of a material in a sample
Sealer mechanism for a tool for applying a seal to overlapping lengths of strap
Thread spool and bobbin holder
Variable valve drive mechanism and intake air amount control apparatus of internal combustion engine
Progesterone receptor modulators
Faucet and handle set
Image pickup apparatus with supervision of noise level differences between fields
Labeling machine with improved cutter assembly