Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Dual ported content addressable memory cell and array










Image Number 8 for United States Patent #5226005.

An improved CAM (content addressable memory) cell is provided with dual address lines operable independently for a Read operation or for a Write operation. The cell is additionally provided with dual ports so that the first port permits a data input for Write operations or alternatively a data input for Search-Compare operations. The second port (Data Output) is independently connected to enable Read out of data residing in the cell. Each CAM cell also has a coincidence line (match-hit) output to indicate when an input Search bit or word coincides with resident data within the CAM cell. The CAM cells are arranged in an array of "m" rows with each row having "n" bits to hold a "n" bit word. Operationally the array permits both "Read" and "Search-Compare" operations to be accomplished in one clock cycle rather than the usual requirement of 3-4 clock cycles.








 
 
  Recently Added Patents
Fail-safe upgrading of portable electronic device software
Method and system for network configuration for virtual machines
Distylium plant named `PIIDIST-I`
Methods for detecting DNA-binding proteins
Dimmer system and damper circuit thereof
Method, apparatus and article for detection of transponder tagged objects, for example during surgery
Formwork release composition and use thereof
  Randomly Featured Patents
Method for diagnosing serum deficiencies
Dispensing applicator
Apparatus for electronically controlled holograms
Signal router with cross-point view graphical interface
Buried air dielectric isolation of silicon islands
Process and device for aligning and co-processing flaccid workpiece layers
Access control to block storage devices for a shared disk based file system
Wall panel assembly
System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit
Field effect transistor, logic circuit including the same and methods of manufacturing the same