Image Number 6 for United States Patent #5196920.
A semiconductor integrated circuit device having semiconductor integrated circuit blocks disposed close to each other. An insulating layer is interposed between each adjacent pair of the semiconductor integrated circuit blocks. An electroconductive shield member is formed between the adjacent semiconductor integrated circuit blocks to limit the capacitive coupling therebetween. The shield member is electrically insulated from the semiconductor integrated circuit blocks and is maintained at a predetermined fixed potential.
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