Resources Contact Us Home
Semiconductor memory device wired to accommodate increased capacity without increasing the size of the semiconductor memory device

Image Number 7 for United States Patent #5195053.

A boundary region for wiring is provided by expanding one of a plurality of boundary regions boundary regions each being between adjacent ones of a plurality of decoder circuits included in a decoder circuit block corresponding to a memory cell array by shifting a desired portion of at least one of the decoder circuits by a desired distance and a wiring connecting wirings in the decoder circuit to a circuit provided outside the decoder circuit block is arranged in the boundary region for wiring, so that a circuit arrangement in a second region outside the decoder circuits can be made freely.

  Recently Added Patents
Memory interface circuit, memory interface method, and electronic device
Liquid-level sensor
Illuminating device
Encoder that detects positional information of a moving body generating interference fringes that move in opposite directions
System and method for providing security in browser-based access to smart cards
Control method and allocation structure for flash memory device
Scalable encoding apparatus, scalable decoding apparatus, scalable encoding method, scalable decoding method, communication terminal apparatus, and base station apparatus
  Randomly Featured Patents
Depth measurement of slickline
Gram load adjusting system for magnetic head suspensions
Wavelength-division multiplexing in passive optical networks
Card management system and method
Process for producing optically active ethyl (3R, 5S, 6E)-7-[2-cycloproply-4-(4-fluorophenyl)quinolin-3-yl]-3,5-dihydroxy-6-hept enoate
Guide shaft tilt adjusting apparatus for optical disc player
Method for producing a beta-processed alpha-beta titanium-alloy article
Sigmoid notch implant
Apparatus for shingling stack of flat articles
Rebuilding a first and second image based on software components having earlier versions for one or more appliances and performing a first and second integration test for each respective image