Image Number 4 for United States Patent #5163090.
An over-current verifier circuit used in a Subscriber Line Interface Circuit (SLIC) for validating an over-current condition on a subscriber loop comprising a first counter connected to the SLIC disposed to receive an oversense signal from the SLIC. The first counter begins counting when the oversense signal is received and produces an output signal when the oversense signal is still active after the counter finishes, denoting a dc over-current in the subscriber loop. A timer circuit connected to the SLIC also receives the oversense signal. The timer is arranged to begin counting when the oversense signal is received. A second counter further receives the oversense signal and is advanced by one count on the high to low transition of the oversense signal. The second counter produces an output signal when three counter advances are produced before the timer times out, denoting an ac over-current condition. A register circuit connected to the first counter and to the second counter is arranged to receive the first counter output signal or the second counter output signal and transmit to a logic interface an over-current signal advising a central controller that an over-current condition exists on the subscriber loop. Finally, a cut clear pulse generator connected to the register circuit and to a cut relay is also arranged to receive the over-current signal from the register circuit and produce an output pulse that enables the cut relay. The cut relay then electrically breaks the subscriber loop, isolating the SLIC from the subscriber loop.