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Error-bit generating circuit for use in a non-volatile semiconductor memory device










Image Number 3 for United States Patent #5142541.

An error-bit generating circuit for use in a nonvolatile semiconductor memory device, particularly in an EEPROM. The circuit is capable of easily checking the deterioration of operational performance in an error checking correction device thereof, by intentionally writing bit-error data into a memory cell thereof. The error-bit generating circuit includes a parity generator for generating specified bits of parity data according to input data received from an input buffer, means for writing into a memory cell array the input data and parity data, means for, after reading out the input data and parity data from the memory cell array, correcting an error-bit among the input data and then providing the corrected data, and an error-bit generator coupled between the input buffer and the memory cell array, for generating an error-bit signal onto a selected bit of the input data in response to a control signal and an address signal.








 
 
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