Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Circuit for repairing defective bit in semiconductor memory device and repairing method










Image Number 5 for United States Patent #5134585.

A circuit for repairing a defective memory cell is provided between a row or column decoder and a memory cell array. When the decoder has n output lines, the memory cell array includes at least (N+1) row or column lines, where n is an integer. The repair circuit includes connection circuit for connecting the output lines of the decoder to the row or column lines, and a circuit for defining the connection of the connection circuit. The connection circuit includes n switching elements each of which is operable to connect one output line of the decoder to at least two row or column lines. The defining circuit defines the connection path of each switching element such that the output lines of the decoder is connected in one to one correspondence to successively located row or column lines excluding a row or column line connecting a defective memory cell. The defining circuit includes a series of laser programmable fuse elements provided between an operation voltage supply and a ground line. The repair circuit occupies a reduced area of a chip because of no spare decoder and no program circuit and it carries out a reliable and fast memory repair because of the reduced number of the fuse elements to be blown off.








 
 
  Recently Added Patents
Area efficient through-hole connections
Compositions and processes for forming photovoltaic devices
Light-reflective anisotropic conductive paste and light-emitting device
Vacuum cleaner
Acoustic measuring instrument
Method to quantify siRNAs, miRNAs and polymorphic miRNAs
Method and system for reduction of decoding complexity in a communication system
  Randomly Featured Patents
Process for preparing flexible foams
Dual spout container
Wireless email communications system providing resource updating features and related methods
Zoom compact camera
Slow release formulations comprising anionic polysaccharide
Semiconductor device with pillar-shaped capacitor storage node
Pressure-resistant hose using polyethylene fabrics
Electrical apparatus system
Stressed field effect transistor and methods for its fabrication
Apparatus for the purpose of avoiding pressure drop between a gaseous or vaporous phase and a liquid phase