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Manufacturing method of well region in coms intergrated circuit

Image Number 7 for United States Patent #5114868.

First, N-type channel stoppers are formed in an element formation region of a P-channel MOS transistor and in an element isolation region of the P-channel MOS transistor, of a CMOS transistor. After forming a field oxide film, an N well is formed in the element formation region of the P-channel MOS transistor. In spite of the fact that the dose of ions used for the formation of an N-type channel stopper is smaller than the dose of ions used for the formation of an N well, the surface concentration of the N-type impurity of the N-type channel stopper is higher than that of the N well. The N-type impurity concentration in the portion where the N-type channel stopper and the N well are brought into contact, becomes uniform. The variability in the threshold voltage of the P-channel MOS transistor, the threshold voltage of the P-channel parasitic MOS transistor, the junction breakdown voltage of the P.sup.+ diffused layer and the junction capacitance of the P.sup.+ diffused layer is reduced, so that the device obtained is suited for the submicron process.

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