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Method and apparatus for absolute value summation and subtraction

Image Number 4 for United States Patent #5084835.

In an absolute value subtraction processing of .vertline.X-Y.vertline., carry generation and propagation functions and group carry generation and propagation functions are first generated. Then, a carry is calculated at the most significant bit in the summation of a first operand and a complement of "2" of a second operand by use of the above functions. Where the carry is "1", the above summation remains continued. Where the carry is zero, additional first and second functions are generated by inverting logic ORs of the carry generation and propagation functions and of the group carry generation and propagation functions. Thus, the summation of the second operand and a complement of "2" of the first operand is realized by use of the additional functions, the carry propagation function, and the group carry propagation function.

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