Resources Contact Us Home
Browse by: INVENTOR PATENT HOLDER PATENT NUMBER DATE
 
 
Circuit for eliminating metastable events associated with a data signal asynchronous to a clock signal










Image Number 2 for United States Patent #5036221.

A circuit for reducing the metastable events produced by a data signal asynchronous to a system clock signal is provided. The circuit includes an edge detector (32) for detecting a transistion of the data signal. The edge detector (32) controls a clock disable/reenable circuit (46) which will disable a system clock directed to a clocked device (36). The period of disablement is the minimum setup time for the clocked device (36). After the minimum setup time has passed, the disable/reenable circuit (42) will reenable the system clock to the clocked device (36). The system clock may be modified by a duration limit circuit (68). Data directed to the clocked device (36) may be delayed via a delay circuit (70).








 
 
  Recently Added Patents
Method and apparatus for using virtual machine technology for managing parallel communicating applications
Techniques for distributed storage aggregation
Developing device
Database caching utilizing asynchronous log-based replication
Battery cell separator
Polypeptides having beta-glucosidase activity and beta-xylosidase activity and polynucleotides encoding same
Account managing device, image processing system, and storage medium
  Randomly Featured Patents
Portable telephone having removable transducer
Level translator circuit for power supply disablement
N-heterocyclic derivatives as NOS inhibitors
Memory management in network processors
Seal member, assembly and method
Pigmented compositions and methods for producing radiation curable coatings of very low gloss
Idling speed control system of an internal combustion engine
Semiconductor device having sense amplifier including paired transistors
Hard disk drive carrier latch apparatus
Method and apparatus for bi-directional transfer of data between two buses with different widths