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Programable logic array using one control clock signal










Image Number 5 for United States Patent #5010258.

A programmable logic array PLA is operated under control of a single-phase clock in which a fixed current does not flow in one of an AND array and an OR array in the PLA while the other of the AND array and the OR array is precharged. Thus, this PLA can realize low consumption of electric power and a high clock frequency, thereby enabling high-speed operation.








 
 
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