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Method for manufacturing semiconductor rectifier










Image Number 2 for United States Patent #4977107.

Rectifiers of excellent characteristics may be more economically fabricated by a process in which a cavity is first etched in a non-epitaxial semiconductor wafer to a depth in the range of typically 15-25 percent of the initial wafer thickness. Simultaneous diffusion of N and P type dopants is used to provide (for an N type substrate) a P+ region in the bottom of the cavity and surrounding surface, and an N+ region on the opposite face of the wafer. A mask is then provided in the cavity bottom and the surrounding wafer regions etched to remove the P+ dopant outside the cavity thereby re-exposing the surrounding region of the original N type substrate. The P+ region may be level with or protrude slightly from the substrate surface. The junction formed between the P+ region in the cavity bottom and the N type substrate has a gradual contour where it intersects the surface thereby providing a more favorable field distribution. Passivation and metallization are provided in the conventional manner. The resulting devices may be fabricated in very thin wafers without significant mechanical breakage loss.








 
 
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