Image Number 3 for United States Patent #4908683.
The problem of unwanted residual polysilicon stringers along the sidewalls of a field oxide layer employed in direct moat wafer processing is avoided by a processing scheme in which the sidewalls of the aperture in the field oxide layer are initially tapered prior to formation of the polysilicon layer to be used for the gate electrode(s). Because of the graduated thickness of the sidewalls of the field oxide layer, the thickness of the polysilicon layer formed thereon is substantially uniform over the entirety of the substrate. As a result, during subsequent masking of the polysilicon layer to define the gate electrode(s), all unmasked portions of the polysilicon are completely etched, leaving no residual material (e.g. stringers) that could be a source of device contamination. After the polysilicon gate has been delineated, the sloped sidewalls of the field oxide are removed (by anisotropic etching), so that the sidewalls of the apertures or windows of the field oxide layer will be perpendicular to the planar surface of the substrate, thus facilitating proper formation of dielectric (oxide) spacers therealong, which thereby provide separation between contact materials and the junction created by shallow ion implantation of dopants through the field oxide aperture.