Image Number 4 for United States Patent #4879692.
A dynamic type memory circuit is provided with an improved write circuit which can write a desired data signal to a memory cell in a selected column in a first mode and to a plurality of memory cells in all the columns simultaneously in a second mode. The memory circuit includes a plurality of memory cell groups, a plurality of sense amplifier groups provided for the memory cell groups, a write circuit for operatively writing an input data signal to a plurality of memory cells simultaneously in at least one memory cell groups and a plurality of independent sense amplifier activation circuits provided for the sense amplifier groups.
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