Image Number 14 for United States Patent #4825452.
The present invention provides a digital frequency shift keying (FSK) demodulator circuit which receives a hard-limited FSK input signal and recovers the modulating baseband signal at 300 baud or less. The FSK demodulator includes a digital phase locked loop demodulator section which receives the FSK input signal and generates a pulse width modulated output the frequency of which is a function of the input signal frequency. The output of the PLL demodulator section is provided to a quantizer which generates a set of parallel numbers. A translating means, for example a code linearizer, converts the parallel numbers into corresponding parallel outputs which are representative of the frequency of the FSK input signal. The parallel outputs are processed by a digital filter which emulates a second-order, low-pass filter. The filter processes the parallel outputs utilizing pulse density modulation. A deglitcher removes noise from the filter output to provide the demodulated data output.