Resources Contact Us Home
Semiconductor memory device having test pattern generating circuit

Image Number 7 for United States Patent #4821238.

A semiconductor memory device comprises an internal circuit including a memory circuit; a test pattern generating circuit; an element for receiving external signals supplied from the outside; and an input switching circuit connected between the test pattern generating circuit and the receiving element, for switching the input supplied to the internal circuit between output signals generating from the test pattern generating circuit and the external signals, the output signals generated from the test pattern generated circuit being input to the internal circuit through the input switching circuit in a test mode, the external signals being input to the internal circuit through the input switching circuit in a usual mode; the test pattern generating circuit, the input switching circuit, and the internal circuit being provided on the same chip.

  Recently Added Patents
Fuel cell stack including ejector and blower for anode recirculation and method for controlling the same
Interlock apparatus for vacuum circuit breaker
Method and apparatus for storing email messages
Fire detector
Mirror elements for EUV lithography and production methods therefor
Multi-channel memory system including error correction decoder architecture with efficient area utilization
Method for computer-based determination of a position in a map, navigation device and mobile radio telephone
  Randomly Featured Patents
Method for cooling meals and stirring device embodied as heat exchanger
Methods of adding reactive metals to form a remelting electrode
Fire extinguishing systems and methods
Disposable foot protector
Ink jet recording apparatus and method
Container opener
Sealing arrangement for a rotor of a turbo machine
Multi-beam scanning system with sync signal generation based on single beam detection
Handheld computing device